What OSATs Do
Outsourced Semiconductor Assembly and Test (OSAT) companies take bare silicon dies from foundries and turn them into finished, tested chips ready for mounting on circuit boards. The process involves die attach (bonding the silicon to a substrate or leadframe), wire bonding or flip-chip interconnection, molding or encapsulation, marking, and final electrical testing. It's the last mile of semiconductor manufacturing, and it's handled by a specialized industry segment that most people outside the chip business have never heard of.
The OSAT market is worth about $42 billion annually, representing roughly 7% of the total semiconductor industry. It's a lower-margin business than chip design or foundry manufacturing — gross margins typically run 25-35% compared to TSMC's 55%+ — but it's essential infrastructure that enables the fabless semiconductor business model.
The Major Players
The OSAT industry is concentrated among a handful of large players, mostly headquartered in East Asia:
- ASE Technology Holding — the largest OSAT by revenue (about $17 billion), headquartered in Kaohsiung, Taiwan. ASE merged with Siliconware Precision Industries (SPIL) in 2018 to create a dominant player. They handle packaging and testing for Apple, Qualcomm, and many other major chip companies.
- Amkor Technology — second largest, headquartered in Arizona but with primary operations in South Korea, China, and Vietnam. Amkor is the go-to OSAT for many US fabless companies. Revenue about $7 billion.
- JCET Group (Jiangsu Changjiang Electronics Technology) — China's largest OSAT, based in Jiangyin. Acquired Singapore's STATS ChipPAC in 2015, gaining advanced packaging capabilities. Revenue about $5 billion.
- Powertech Technology (PTI) — Taiwan-based, focused on memory packaging. Major supplier to Micron and other memory companies.
- Tongfu Microelectronics — Chinese OSAT that acquired AMD's Suzhou and Penang packaging operations in 2016.
Below these top tier, there are dozens of smaller OSATs serving specific markets or regions. The industry has been consolidating through M&A, with the top five companies accounting for about 65% of total OSAT revenue.
Package Types and Technology Progression
Semiconductor packages have evolved enormously from the simple plastic DIPs (dual in-line packages) of the 1970s. Modern packages are complex multi-layer structures that manage power delivery, signal integrity, thermal dissipation, and mechanical protection simultaneously.
Related reading: Storage Controller Architecture: NVMe, UFS, and Computationa.
The major package categories in use today:
- Leadframe packages (QFN, QFP, SOIC) — the workhorse of the industry for cost-sensitive applications. A QFN package costs a few cents and is suitable for microcontrollers, power management ICs, and simple analog chips.
- Laminate substrate packages (BGA, LGA, FC-BGA) — used for processors, FPGAs, and complex SoCs. The die is flip-chip bonded to a multi-layer organic substrate with hundreds or thousands of solder ball connections. An FC-BGA package for a data center processor might cost $10-50.
- Wafer-level packages (WLCSP, fan-out WLP) — the package is built directly on the wafer before dicing, eliminating the separate substrate. Common for small, low-pin-count devices like RF filters, power management ICs, and MEMS sensors.
- Advanced packages (2.5D, 3D, fan-out with high-density interconnect) — the frontier of packaging technology, discussed in more detail below.
The Advanced Packaging Revolution
Advanced packaging is where the OSAT business is being disrupted. Technologies like TSMC's CoWoS (Chip on Wafer on Substrate), Intel's Foveros, and various fan-out and 3D packaging approaches are blurring the line between foundry and OSAT services.
TSMC's CoWoS is the packaging technology behind NVIDIA's H100 and B200 AI accelerators. It places multiple dies (the GPU die plus HBM memory stacks) on a silicon interposer that provides fine-pitch interconnections between them. The interposer is manufactured using semiconductor-grade lithography — essentially, it's a chip itself — which means the packaging is done in a wafer fab, not a traditional OSAT facility.
This is a fundamental shift. When the packaging technology requires semiconductor-grade manufacturing capability, the foundries have a natural advantage over traditional OSATs. TSMC has invested billions in advanced packaging capacity and keeps it tightly integrated with their fab operations. ASE and Amkor are investing in their own advanced packaging capabilities, but they're playing catch-up in technologies like silicon interposers and hybrid bonding.
For a related perspective, see EDA Tool Landscape: Synopsys, Cadence, Siemens, and Open-Sou.
Where OSATs Still Dominate
Despite the foundry encroachment on advanced packaging, traditional OSATs still handle the vast majority of semiconductor assembly and test. Most chips don't need CoWoS or Foveros — they need reliable, cost-effective packaging at scale. Wire-bonded QFN packages, standard flip-chip BGA, and conventional wafer-level packaging are bread-and-butter OSAT services that foundries have no interest in competing for.
Testing is another area where OSATs maintain a strong position. Final test — applying electrical stimulation to every pin of a packaged chip and verifying functionality — requires expensive automated test equipment (ATE) from companies like Advantest and Teradyne. OSATs invest heavily in ATE fleets and testing expertise. The test data they generate also feeds back into yield improvement for their customers and the foundries.
Geographic Distribution and Risk
OSAT operations are concentrated in a few countries:
- Taiwan — ASE/SPIL's primary operations
- China — major operations for JCET, Tongfu, and significant factories for ASE and Amkor
- South Korea — Amkor's largest operations
- Malaysia — historically a major OSAT location (Intel, Infineon, and others have in-house packaging here)
- Vietnam — growing as a packaging destination. Amkor opened a major facility in Bac Ninh, and Samsung has packaging operations in Thai Nguyen
The geographic concentration creates supply chain risk similar to the foundry situation, though less acute because packaging technology is less differentiated than leading-edge fab processes. Building a new packaging facility takes 12-18 months, versus 3+ years for a new fab, so capacity can be rebalanced more quickly.
We covered a related topic in High-NA EUV Lithography: The Next Step Beyond Current EUV fo.
The Testing Side
Semiconductor testing happens at two stages: wafer probe (testing dies before they're packaged) and final test (testing the finished packaged chip). Both are critical for ensuring quality and yield.
Wafer probe uses probe cards — precision-manufactured arrays of tiny needles that contact the pads on each die. Modern probe cards for advanced processors have thousands of probe tips that must simultaneously make contact with a die's pads to within a few microns of accuracy. The probe card itself can cost $50,000-200,000 and wears out after testing a few thousand wafers.
Final test throughput is a major cost driver. A high-end ATE system from Advantest or Teradyne costs $2-5 million and can test one to a few devices at a time, depending on the chip's pin count and test complexity. Test time ranges from milliseconds for simple parts to minutes for complex processors that require extensive at-speed testing. Reducing test time by even 10% can save millions of dollars annually across a high-volume product.
The Future: Integration and Consolidation
The OSAT industry faces a strategic inflection point. On one side, foundries are pulling advanced packaging in-house. On the other, the IDMs (Intel, Samsung, TI) have always done their own packaging and testing. OSATs are being squeezed from both directions.
The response is consolidation (the ASE-SPIL merger being the clearest example) and technology investment. OSATs that can offer advanced packaging capabilities — high-density fan-out, panel-level packaging, hybrid bonding — will capture the growing market for chiplet-based designs that need advanced interconnect but don't necessarily need TSMC-level silicon interposers.
Panel-level packaging is one area where OSATs might find an advantage. Instead of processing packages on 300mm round wafers (the foundry standard), panel-level packaging uses large rectangular panels (like PCB panels) that offer much better area utilization and lower cost per unit. ASE and several others are investing in panel-level fan-out technology that could dramatically reduce advanced packaging costs for high-volume applications.