EUV Lithography Explained
The Light That Builds Modern Chips

What Is EUV Lithography?

EUV lithography (Extreme Ultraviolet Lithography) is a photolithography technique that uses light with a wavelength of 13.5 nanometers to etch incredibly fine circuit patterns onto silicon wafers. It is the critical enabling technology for manufacturing chips at 7nm and below.

To appreciate why EUV matters, consider the fundamental challenge of chip manufacturing: you need to project circuit patterns — billions of transistors, each smaller than a virus — onto a flat silicon surface with sub-nanometer precision. The physics of light diffraction means you cannot print features much smaller than the wavelength of light you use.

The wavelength problem

* 7nm achieved through multi-patterning (printing the same layer multiple times), which adds cost and complexity.

EUV's 13.5nm wavelength represents a 14.3x improvement over ArF immersion's effective wavelength, enabling single-exposure patterning of features that previously required 3–4 separate exposure passes.

How EUV Works: From Tin Droplets to Transistors

Generating 13.5nm light is extraordinarily difficult. Unlike DUV systems that use excimer gas lasers, EUV requires an entirely different approach — one that borders on controlled nuclear physics.

Step 1: Generating EUV light

The light source is the most technically challenging component:

1. Tin droplet generation: A tin (Sn) generator produces molten tin droplets approximately 25 micrometers in diameter, falling at a rate of 50,000 droplets per second.
2. Pre-pulse laser: A lower-power CO₂ laser pre-pulse hits each droplet, flattening it into a thin pancake shape to maximize surface area.
3. Main pulse vaporization: A high-power CO₂ laser (25+ kW) strikes the flattened tin, superheating it to approximately 500,000°C — creating a plasma that emits EUV radiation at exactly 13.5nm wavelength.
4. Collector mirror: A large multilayer collector mirror (composed of alternating layers of molybdenum and silicon, each just a few nanometers thick) captures and focuses the EUV light.

Step 2: Optics — all mirrors, no lenses

At 13.5nm, virtually all materials absorb light rather than transmitting it. This means EUV cannot use traditional glass lenses. Instead, the entire optical path uses reflective mirrors coated with multilayer stacks of molybdenum and silicon (Mo/Si), achieving about 70% reflectivity per surface.

A standard EUV scanner uses 6 mirrors in its projection optics. With 70% reflectivity per mirror, only 0.7⁶ ≈ 12% of the light reaches the wafer. This optical loss drives the need for extremely bright EUV sources.

Step 3: Patterning

The EUV light reflects off a photomask (also reflective, not transmissive like DUV masks) carrying the circuit pattern. The pattern is projected onto a photoresist-coated silicon wafer at 4:1 demagnification — meaning mask features are 4x larger than the final printed pattern.

The wafer stage positions the wafer with sub-nanometer accuracy while the scanner exposes each field at speeds of up to 185 wafers per hour (current generation).

DUV vs EUV: Why the Switch Was Necessary

Before EUV, the semiconductor industry extended DUV lithography far beyond its theoretical limits through a technique called multi-patterning. Understanding why this approach hit its wall explains why EUV was worth three decades of development.

The multi-patterning trap

Multi-patterning prints the same layer in multiple passes, splitting a dense pattern into sparser sub-patterns that DUV can resolve. At 7nm, this required Self-Aligned Quadruple Patterning (SAQP) — four lithography-etch cycles for a single metal layer.

Each additional pass introduces overlay errors (alignment between passes), increases cycle time, and raises costs. By the time foundries reached 5nm, some critical layers required SAQP + cut masks + via patterning — turning what should be a single step into a cascade of 6-8 process steps.

EUV solved this by replacing multi-pass DUV with single-exposure patterning, reducing both cost and defect density at advanced nodes.

High-NA EUV: The Next Leap

Standard EUV (NA = 0.33) is reaching its resolution limits at the 2nm node. The next generation, High-NA EUV (NA = 0.55), pushes resolution further by increasing the numerical aperture of the projection optics.

What is Numerical Aperture?

Numerical Aperture (NA) determines the smallest feature a lithography system can resolve. The Rayleigh equation governs this:

ASML EXE:5000 specifications

Intel received the first High-NA EUV system in late 2024 for its Intel 14A process (expected 2026-2027). TSMC plans to use High-NA EUV for its A14 (1.4nm) node in 2027-2028.

The half-field challenge

Increasing NA from 0.33 to 0.55 required larger mirrors, but ASML could not scale the mask size proportionally. The result is a halved field size — each exposure covers only half the area of a standard EUV exposure. For chips larger than the half-field, two exposures must be "stitched" together, adding complexity and potential alignment errors.

ASML's Global Monopoly

ASML Holding N.V., headquartered in Veldhoven, Netherlands, is the sole manufacturer of EUV lithography systems in the world. This isn't a market position — it's a technological monopoly built over 30+ years of investment.

Why no one else can build EUV machines

• Light source: Developed with Cymer (acquired by ASML in 2013 for $3.7B), requiring decades of plasma physics expertise
• Optics: Only Carl Zeiss SMT can produce the atomically flat mirrors required — surface roughness must be below 0.05nm (a few atoms)
• Vacuum systems: The entire optical path must operate in near-perfect vacuum to prevent EUV absorption
• Integration: Over 100,000 parts from 5,000+ suppliers, with no single alternative source for most critical components

Geopolitical implications

ASML's monopoly makes it a central piece in the U.S.–China semiconductor competition. Under pressure from the U.S., the Netherlands has restricted EUV exports to China since 2019. In 2024, restrictions expanded to include some DUV systems (TWINSCAN NXT:2050 and newer).

China's largest chipmaker, SMIC, operates without EUV, limiting its most advanced production to approximately 7nm using DUV multi-patterning — a costly and yield-challenged approach that cannot economically scale to 5nm or below.

Cost and Throughput Challenges

The economics of EUV

Despite the higher per-exposure cost, EUV is economically favorable at 5nm and below because it eliminates multi-patterning overhead. A single EUV exposure replaces 3-4 DUV exposures, reducing total process steps, defect opportunities, and cycle time.

Throughput evolution

EUV throughput has improved steadily as light source power increased:

• 2019 (NXE:3400B): ~125 wafers per hour (wph), 250W source
• 2022 (NXE:3600D): ~160 wph, 400W source
• 2024 (NXE:3800E): ~185 wph, 500W+ source
• 2026+ target: 200+ wph, 600W+ source

Higher source power means more photons per exposure, allowing faster scanning without sacrificing pattern quality.

How EUV Enables 2nm Chips

The transition to 2nm chips relies on EUV in two fundamental ways:

1. Patterning GAA nanosheet transistors

The Gate-All-Around (GAA) nanosheet architecture at 2nm requires patterning features at 12-16nm half-pitch for critical metal layers. Without EUV, this would require octuple patterning with DUV — practically impossible to manufacture at commercial yields.

EUV enables single or double-exposure patterning for these critical layers, keeping the process economically viable.

2. Backside Power Delivery Networks

2nm chips from Intel (PowerVia) and eventually TSMC (Super Power Rail) route power lines through the back of the chip. These backside features still require precision lithography — EUV provides the resolution needed to pattern power delivery vias on the wafer backside.

EUV layers at each node

At 2nm, over a third of all lithography layers use EUV, up from less than 10% at 7nm. This underscores EUV's transition from optional enhancement to manufacturing necessity.

The Future of Lithography

Near-term: High-NA EUV (2025–2028)

High-NA EUV will enable nodes at 1.4nm (TSMC A14, Intel 14A), pushing single-exposure resolution below 8nm half-pitch. The half-field challenge will be addressed through stitching techniques and chip design adaptations.

Medium-term: Hyper-NA EUV (2030+)

ASML is researching Hyper-NA systems (NA > 0.70) that would extend EUV to sub-1nm nodes. However, increasing NA further introduces severe optical aberrations and even smaller field sizes. Anamorphic optics — mirrors with different magnification in X and Y directions — may be required.

Computational lithography

AI and computational methods are increasingly important for pushing resolution beyond optical limits:

• Inverse Lithography Technology (ILT): Using GPU-accelerated computation to optimize mask patterns, turning simple circuit shapes into complex "curvilinear" mask features that produce better printed results
• Source-mask optimization (SMO): Co-optimizing the illumination source shape and mask pattern simultaneously
• Machine learning for defect detection: AI models that predict and compensate for systematic patterning errors

Beyond EUV?

Some researchers are exploring alternative approaches for the post-EUV era:

• Directed Self-Assembly (DSA): Using block copolymers that naturally form nanoscale patterns — potentially augmenting lithography for regular structures
• Nanoimprint Lithography: Canon's approach using physical molds — lower cost but limited to specific applications like NAND flash
• Multi-beam electron lithography: Direct-write patterning without masks — high resolution but extremely slow for production volumes

None of these is positioned to replace EUV for leading-edge logic manufacturing. For the foreseeable future, EUV and its High-NA successor remain the only path to sub-2nm chips.

Frequently Asked Questions

Conclusion

EUV lithography represents one of humanity's most complex engineering achievements — a machine that generates plasma hotter than the sun's surface, focuses light through atomically perfect mirrors in a vacuum, and prints patterns smaller than a virus, 185 times per hour, on a surface flatter than any natural object on Earth.

As the semiconductor industry pushes toward 2nm and beyond, EUV and its High-NA successor remain the irreplaceable foundation. Every smartphone processor, every AI accelerator, and every datacenter chip manufactured at advanced nodes passes through an ASML EUV scanner — making this technology one of the most consequential chokepoints in the global economy.