The Three Companies That Control Chip Design Software
Designing a modern semiconductor requires electronic design automation (EDA) software at every step — from writing RTL code to verifying the design to laying out the physical chip to signing off for manufacturing. Three companies supply virtually all of this software: Synopsys, Cadence Design Systems, and Siemens EDA (formerly Mentor Graphics, acquired by Siemens in 2017).
Their combined market share exceeds 85%. Revenue in 2024: Synopsys about $6.1 billion, Cadence about $4.1 billion, Siemens EDA roughly $2 billion (estimated, since Siemens reports it within a larger business unit). Together, that's $12+ billion in annual revenue to enable a $600 billion semiconductor industry. The apply is remarkable — every dollar spent on EDA tools enables roughly $50 of chip production.
Synopsys: The Full-Stack Leader
Synopsys is the largest EDA company and has the broadest product portfolio. Their key products span the entire design flow:
- Design Compiler — the industry-standard logic synthesis tool that converts RTL (Verilog/VHDL) into a gate-level netlist. Most chip designs worldwide go through Design Compiler at some point.
- Fusion Compiler — their unified place-and-route and optimization platform, increasingly replacing the older IC Compiler II for advanced nodes
- PrimeTime — the gold standard for static timing analysis. When your design has to meet timing at 3GHz on a 3nm process, PrimeTime is what tells you if it does.
- VCS — the most widely used Verilog/SystemVerilog simulator for functional verification
- StarRC — parasitic extraction tool that models the electrical effects of the physical wiring
- IC Validator — physical verification (DRC, LVS) that checks whether your layout follows the foundry's design rules
Synopsys also has a massive IP business (DesignWare) and acquired Ansys in 2024 for about $35 billion, adding multi-physics simulation capabilities that are increasingly important for power, thermal, and electromagnetic analysis of advanced chips.
Cadence: Strong in Analog and Custom Design
Cadence's strengths are in custom/analog design and physical implementation:
This connects to the ideas in Data Center Accelerators: GPUs, FPGAs, and Custom ASICs for .
- Virtuoso — the dominant tool for analog and mixed-signal circuit design. If you're designing an ADC, a PLL, or an op-amp, you're almost certainly using Virtuoso's schematic editor and layout environment.
- Innovus — their digital place-and-route tool, which competes head-to-head with Synopsys' Fusion Compiler
- Xcelium — simulation platform for digital verification, competing with Synopsys' VCS
- Spectre — the standard SPICE simulator for analog circuit analysis. Spectre FX adds distributed computing for post-layout simulation of large circuits.
- Tempus — their static timing analysis tool, competing with PrimeTime
- Pegasus — physical verification tool
Cadence has been growing faster than Synopsys in recent years, partly driven by expansion into system-level analysis (their Clarity 3D solver for electromagnetic simulation and Celsius for thermal analysis) and a strong push into the AI-driven EDA space.
Siemens EDA: The PCB and Verification Specialist
Siemens EDA (formerly Mentor Graphics) is the smallest of the three but has strong positions in specific areas:
- Calibre — the most widely used physical verification tool, trusted for DRC and LVS sign-off at advanced nodes. Many foundries specify Calibre as the reference tool for their design rules.
- Questa — their verification platform, which has strong adoption for formal verification and assertion-based verification
- Xpedition and HyperLynx — PCB design and signal integrity tools. Siemens is the dominant player in PCB-level EDA.
- Tessent — design-for-test (DFT) tools for inserting scan chains and generating test patterns. Strong market share in automotive and high-reliability applications.
Siemens' broader industrial software portfolio gives them a unique angle — they can offer chip-to-system simulation that integrates EDA with mechanical CAD, thermal analysis, and manufacturing simulation in ways that standalone EDA companies can't easily replicate.
The AI Revolution in EDA
Machine learning is changing how EDA tools work, and it's the most active area of competition among the big three. The key applications:
This connects to the ideas in Semiconductor Metrology: How Chip Features Are Measured at t.
ML-driven place and route — training models on past designs to predict better floorplans and routing strategies. Google's 2021 Nature paper on using reinforcement learning for chip floorplanning generated enormous attention, though the actual impact on production design flows has been debated. Synopsys' DSO.ai and Cadence's Cerebrus use similar ML-guided optimization approaches that explore the design space more efficiently than traditional heuristics.
Verification closure — using ML to prioritize which tests to run, predict which design areas are most likely to contain bugs, and identify coverage holes. This is arguably where AI has the most practical impact today, because verification consumes 60-70% of the total chip design effort and anything that reduces wasted simulation cycles has huge economic value.
Analog design automation — historically resistant to automation because analog design is more intuitive and less rule-based than digital. ML approaches that learn from existing analog designs to suggest sizing, topology, and layout are starting to emerge, though experienced analog designers are still skeptical that any tool can replace their judgment on sensitive circuits.
Open-Source EDA: Real or Aspirational?
There's a growing open-source EDA ecosystem, driven partly by academic research and partly by frustration with the cost and vendor lock-in of commercial tools. Key projects:
See also: Backside Power Delivery: Why Routing Power Under the Transis.
- Yosys — open-source synthesis tool that handles Verilog elaboration and technology mapping. Widely used in FPGA design and increasingly for ASIC flows.
- OpenROAD — the most ambitious open-source project, aiming to provide a complete RTL-to-GDSII flow. Led by UC San Diego with DARPA funding, it includes placement (RePlAce), routing (TritonRoute), and timing analysis (OpenSTA).
- Magic — venerable open-source layout editor, still used for custom analog and research designs
- ngspice — open-source SPICE simulator, adequate for educational use and small analog circuits
- KLayout — open-source GDS viewer and editor with scripting capabilities
Can open-source EDA replace commercial tools for production chip design? Not today and probably not for advanced nodes in the foreseeable future. The gap in capabilities is enormous — PrimeTime's accuracy at 3nm, Virtuoso's analog layout productivity, Calibre's design rule coverage — these represent decades of cumulative development and close collaboration with foundries. OpenROAD can take a simple design through the flow, but it's not ready for a 10-billion-transistor SoC taping out at TSMC N3.
Where open-source EDA does matter is in education (students can learn chip design without expensive licenses), research (academics can modify and experiment with the tools), and in providing China with a potential alternative path if export controls further restrict access to Western EDA. It's not a replacement for Synopsys and Cadence — it's a complement and, for some users, a necessary fallback.
Pricing and the Customer Relationship
EDA tools are sold primarily through multi-year site licenses called time-based licenses (TBLs). A typical agreement gives the customer access to a bundle of tools for 3 years at a fixed annual fee. Large semiconductor companies pay $50-200 million per year for their EDA tool licenses. Even mid-sized design teams spend $5-20 million annually.
The pricing model creates high switching costs. Once a design team has invested years of learning and infrastructure in one vendor's tools, switching to a competitor requires retraining engineers, re-qualifying the design flow, and accepting risk that the new tools might produce different (possibly worse) results. This stickiness is why EDA companies have some of the highest retention rates and most predictable revenue in the software industry.