Semiconductor IP Licensing and Design Ecosystem
Most people outside the chip industry don't realize that the companies designing chips rarely create every block from scratch. A modern SoC might contain processor cores from ARM, GPU blocks from Imagination Technologies, interface PHYs from Synopsys, memory compilers from a dozen different sources, and analog IP from specialized boutique vendors. This IP licensing ecosystem is the invisible scaffolding beneath almost every chip in your phone, car, and laptop. Understanding how it works gives you a much better picture of why chips cost what they do and why certain architectures dominate.
How IP Licensing Works in Practice
Semiconductor IP (intellectual property) comes in several forms:
- Soft IP — delivered as synthesizable RTL (usually Verilog or VHDL). The licensee takes this RTL, runs it through their own synthesis and physical design flow, targeting their specific foundry process. This gives maximum flexibility but requires the licensee to have strong physical design capabilities.
- Hard IP — delivered as a completed physical layout (GDSII) for a specific foundry and process node. Examples include SRAM compilers, SerDes PHYs, PLL blocks, and standard cell libraries. These are pre-verified for timing, power, and DRC at the target node, saving months of physical design work.
- Firmware/Software IP — the software stack (drivers, BSPs, compilers, middleware) that accompanies hardware IP blocks. ARM's ecosystem strength here is enormous.
The licensing model typically involves an upfront license fee plus a per-unit royalty on each chip shipped. For a high-volume product shipping hundreds of millions of units, the royalty is the dominant cost. For a low-volume product, the upfront license matters more.
ARM's Cortex-A cores illustrate the economics. A license for the Cortex-A78 (a high-performance mobile core) might cost $5-15 million upfront, with royalties of 1-2% of the chip's selling price. For a smartphone SoC selling at $25 and shipping 100 million units, that's $25-50 million per year in royalties. This is why companies like Apple and Qualcomm have invested in designing their own CPU microarchitectures under ARM's architecture license — they pay for the instruction set but do the core design themselves, reducing per-unit royalty to a flat rate or a lower percentage.
The Major IP Vendors
ARM is by far the largest semiconductor IP company, with revenue over $3 billion annually. Their processor cores (Cortex-A, Cortex-R, Cortex-M, Neoverse) are in essentially every smartphone, most embedded systems, and a growing share of servers and PCs. ARM's business model is licensing, not manufacturing — they don't make any chips themselves. The ARM IPO in 2023 valued the company at around $55 billion, reflecting the massive reach of their IP.
ARM offers two license tiers: standard licenses for specific pre-designed cores (Cortex-A720, Cortex-X4, etc.) and architecture licenses that let the licensee design their own microarchitecture using the ARM instruction set. Apple, Qualcomm, Samsung, and Amazon (for Graviton) hold architecture licenses.
Related reading: Silicon Wafer Supply Chain: From Sand to 300mm Wafers.
Synopsys is the second-largest IP vendor and also the leading EDA (electronic design automation) tool company. They supply interface IP (USB, PCIe, DDR, HDMI, MIPI controllers and PHYs), processor IP (ARC cores, ASIP Designer for custom processors), security IP (tRoot, PUF), and a huge catalog of foundation IP (standard cells, memory compilers, I/O libraries) across all major foundries and process nodes.
Synopsys's DesignWare IP portfolio is so comprehensive that it's hard to design a chip without using at least some of it. Their PCIe 6.0 and CXL controller IP, DDR5/LPDDR5X PHYs, and USB4 controllers are used in a significant fraction of new chip designs. In my experience, Synopsys interface PHYs are the safest choice when you can't afford schedule risk — they're well-validated and come with strong foundry support.
Cadence competes directly with Synopsys in both EDA tools and IP. Their Tensilica processor cores (including the widely used HiFi audio DSP and the AI-focused DNA accelerator cores) fill specific niches. Cadence's interface IP (PCIe, DDR, Ethernet) is competitive, and some designers prefer it for specific configurations or foundry targets. Cadence also offers verification IP (VIP) for protocol compliance testing, which is a different but related business.
Imagination Technologies supplies GPU IP (PowerVR), AI accelerator IP (the NNA family), and connectivity IP. They had a rough few years after Apple moved to custom GPU designs, but they've restructured and are finding traction in automotive (Renesas uses PowerVR GPUs in their R-Car platform) and other markets. Their IMGIC ray-tracing GPU IP is interesting for automotive and embedded graphics.
The Foundation IP Layer
Before you can implement any logic on a new process node, you need foundation IP: standard cell libraries, memory compilers, and I/O cells. These are typically developed by the foundry (TSMC, Samsung, Intel) in partnership with IP vendors.
This connects to the ideas in Semiconductor IP Licensing: ARM, Synopsys, and the IP Block .
Standard cell libraries contain hundreds of basic logic gates (NAND, NOR, flip-flops, buffers) in multiple drive strengths and threshold voltage flavors. A modern library for TSMC N3E might have 3,000+ cells across 8-12 track heights. The choice of standard cell library affects area, power, and timing for every block in the chip.
SRAM compilers generate custom memory arrays (caches, register files, buffers) for specific configurations. SRAM bit cell design is one of the hardest problems at advanced nodes — the 6T SRAM cell needs to be reliable across process variation, voltage, and temperature corners. At 3nm, some designs are moving to 8T or even 10T cells for better stability, at the cost of area.
This foundation IP layer is where the foundries have real power. If TSMC's standard cell library for N3 doesn't support the density or power targets you need, your options are limited: work with TSMC to modify the library (expensive, slow), use a third-party library (risky, as foundry support may be weaker), or move to a different process node.
The Economics of Build vs. Buy
Every chip design team faces a constant build-vs.-buy calculus for each block in their SoC. Here's my framework for thinking about it:
Always license when: the block is standardized (PCIe, USB, DDR), the block requires deep analog expertise your team doesn't have (SerDes PHYs, PLLs), or the block requires foundry-specific optimization you can't do yourself (memory compilers).
For a related perspective, see GAA vs FinFET: So Sánh Kiến Trúc Transistor Chi Tiết 2026.
Consider building when: the block is your core differentiator (Apple builds custom CPU cores and GPUs because that's their competitive edge), the licensing costs at your volume make in-house development cheaper over 3-5 years, or the available IP doesn't meet your specific requirements.
The hidden cost of licensed IP is integration. An IP block comes with a data sheet and integration guide, but actually connecting it to your bus fabric, configuring it correctly, validating all the corner cases, and debugging silicon issues still takes significant engineering effort. I've seen projects where integrating and verifying a licensed IP block took almost as long as designing a simpler block would have.
Ecosystem Challenges and Trends
A few things I'm watching in the IP ecosystem:
IP quality and trust are becoming bigger concerns as chips go into safety-critical applications. An automotive chip designer needs IP that comes with FMEDA (Failure Modes, Effects, and Diagnostic Analysis) data, safety manuals, and ISO 26262 assessments. Not all IP vendors provide this, and the quality of safety documentation varies enormously.
RISC-V is disrupting the processor IP market by offering an open instruction set architecture (covered in a separate article). Companies like SiFive, Andes Technology, and Codasip offer commercial RISC-V cores that compete with ARM's Cortex lineup, especially in the microcontroller and embedded space. ARM's revenue isn't declining, but RISC-V is clearly taking share in new designs.
Chiplet IP is an emerging category. As multi-die designs become common, there's a need for die-to-die interconnect IP (UCIe PHYs and controllers), chiplet-level power management IP, and design tools that work across die boundaries. Synopsys and Cadence are both developing chiplet-aware design flows.
The semiconductor IP industry isn't flashy, but it's absolutely critical to the chip ecosystem. Without ARM, there are no smartphones. Without Synopsys DesignWare, most SoCs would take years longer to design. The IP licensing model enables a level of specialization and reuse that has made the current diversity of chip products possible. I don't see that changing — if anything, the trend toward greater complexity and more heterogeneous integration will make IP licensing even more important in the years ahead.