Pushing Resolution Beyond Standard EUV
Standard EUV lithography with a numerical aperture (NA) of 0.33 can reliably pattern features down to about 13nm half-pitch in single exposure. To go smaller — which you need for 2nm nodes and beyond — you have two options: multi-patterning (expensive and complicated) or increase the NA. ASML chose the latter, and the result is the TWINSCAN EXE:5000 series, the first High-NA EUV scanner.
Bumping the NA from 0.33 to 0.55 improves resolution by about 1.7x, enabling single-exposure patterning down to roughly 8nm half-pitch. That's the difference between needing two or three litho passes versus one. For fab economics, that's a very big deal.
The Optical Redesign
Anamorphic Optics
Here's where it gets complicated. Increasing the NA to 0.55 with conventional 4:1 reduction optics would require a mask image field too large to print on a standard 6-inch photomask. ASML's solution was anamorphic optics — the new system uses 4:1 reduction in one direction but 8:1 in the perpendicular direction. This keeps the mask field size manageable but means the exposure field on the wafer is half as wide: 26mm × 16.5mm instead of 26mm × 33mm.
Halving the field width has consequences. Some large dies won't fit in a single exposure — you'd need stitching, where two exposures are butted together. The stitching boundary is a potential yield risk. For most chips, though, the smaller field is workable. A typical processor die fits comfortably within the 26 × 16.5mm field.
Related reading: SoC Design Methodology: Integrating CPU, GPU, NPU, and IO on.
The Mirror Problem
High-NA optics require larger mirrors with even tighter surface figure tolerances than standard EUV. The projection optics box weighs several tons. Zeiss had to develop new figuring and polishing techniques to achieve the sub-50 picometer surface accuracy needed. Each mirror takes months to fabricate and measure.
The larger NA also means the system is more sensitive to aberrations, flare, and stray light. The optical design and the computational lithography (OPC) models both had to be reworked significantly from the standard EUV platform.
Pellicle Challenges
A pellicle is a thin membrane mounted above the photomask to keep particles off the mask surface. For standard EUV, pellicles are already pushing limits — the membrane must be transparent at 13.5nm, which restricts material options to polysilicon or carbon nanotube films a few tens of nanometers thick. These membranes absorb about 10-15% of the EUV light, reducing throughput.
See also: Backside Power Delivery: Why Routing Power Under the Transis.
For High-NA, the situation is worse. The higher NA means light hits the pellicle at steeper angles, and the wider angular range means any wavefront distortion from the pellicle has a bigger impact. Plus, the absorbed EUV energy heats the pellicle, causing it to distort — and the tighter resolution budget means less tolerance for distortion. Running without a pellicle is an option some fabs consider, but it increases mask contamination risk and requires more frequent mask cleaning.
First Installations
Intel received the first High-NA EUV prototype (EXE:5000) at their Hillsboro, Oregon facility in late 2023. TSMC and Samsung have also placed orders. The initial machines are essentially for process development — high-volume production with High-NA isn't expected until 2026-2027 at the earliest.
The tool's price tag is around $350-380 million each. It's larger than a standard EUV scanner, requires dedicated facility infrastructure (the tool weighs about 150 tons), and consumes more power. The source power requirements are higher because the larger optics lose more light, and throughput targets of 185+ wafers per hour demand a very bright source.
For a related perspective, see ARM Architecture Evolution: From ARMv8 to ARMv9 and Custom C.
Impact on Process Design
High-NA doesn't just slot into existing process flows. The smaller depth of focus (a consequence of higher NA) means thinner resist films, tighter wafer flatness requirements, and more demanding focus control. Resist chemistry needs to be reformulated for the thinner films and higher resolution.
There's also a computational challenge. The OPC patterns — the pre-distorted mask designs that compensate for optical effects — become more complex with anamorphic optics. The mask data volume increases, and the computational time for OPC and mask inspection grows. EDA vendors like Synopsys and Cadence have been developing High-NA-aware tools, but the computational cost is significant.
I'd argue that High-NA is the single most important technology development in lithography this decade. It determines whether the industry can continue scaling at reasonable cost, or whether multi-patterning costs spiral out of control. The early results from Intel's prototype will be watched very carefully by the entire industry.