From Mobile Chip to Everything Chip
ARM started as a mobile phone processor architecture. That was the 2000s. Today, ARM cores power everything from $2 microcontrollers to Apple's M4 Ultra workstation chips and NVIDIA's Grace data center CPUs. AWS's Graviton instances run on ARM. Microsoft's Surface laptops run on ARM. The architectural evolution that enabled this expansion — from ARMv8 to ARMv9 and the parallel development of custom core designs — is one of the more interesting stories in modern computing.
ARMv8: The 64-Bit Foundation
ARMv8-A, introduced in 2011, was ARM's transition to 64-bit. The AArch64 execution state brought 31 general-purpose 64-bit registers (up from 15 in 32-bit ARM), a cleaner instruction encoding, a flat 64-bit virtual address space, and NEON SIMD instructions standard on every core. It also maintained backward compatibility with 32-bit ARM code through the AArch32 execution state.
The first ARMv8 cores — Cortex-A53 and Cortex-A57 — shipped in smartphones in 2014. But the architecture's real impact came when companies started designing custom cores based on ARMv8. Apple's Cyclone core (iPhone 5s, 2013) was actually the first ARMv8 silicon to ship, beating ARM's own designs to market. Apple's custom core was wider, faster, and more power-efficient than anything ARM Ltd. offered as a reference design. That set the pattern that continues today.
ARMv9: Security, AI, and Wider Vectors
ARMv9-A, announced in 2021, added three major capability groups:
We covered a related topic in Chip Design Startups: Funding, Time-to-Tapeout, and the RISC.
Scalable Vector Extension 2 (SVE2)
SVE2 is ARM's answer to wide SIMD processing. Unlike fixed-width SIMD (where the vector width is baked into the instruction encoding), SVE uses vector-length agnostic programming. Code written for SVE works on any implementation regardless of whether the hardware has 128-bit, 256-bit, or even 2048-bit vector registers. The same binary runs on all of them, using whatever width the hardware supports.
In practice, most current ARMv9 implementations use 128-bit SVE2 (same width as NEON), so the immediate throughput benefit over ARMv8 is modest. The real payoff comes as future designs widen to 256-bit or more. Apple's cores already implement wider execution engines internally, though they use their own AMX (Apple Matrix Extension) instructions rather than SVE for AI workloads.
Confidential Compute Architecture (CCA)
ARM Realms extend TrustZone's security model to support multiple isolated execution environments. Each Area has its own encrypted memory space that's inaccessible to the hypervisor or other Realms. This is ARM's answer to Intel SGX and AMD SEV — enabling confidential computing in cloud environments where you don't trust the infrastructure provider.
Related reading: Satellite and Space-Grade Chips: Radiation Hardening and Ext.
Matrix Extension (SME)
The Scalable Matrix Extension adds dedicated matrix operations to the ISA — outer products, matrix tile storage, and streaming SVE modes that operate on 2D tile data structures. SME is aimed at AI inference workloads and signal processing. ARM's Cortex-X925 was among the first cores to implement SME.
ARM's Core Lineup
ARM sells processor designs in three performance tiers:
- Cortex-X series (X4, X925): Maximum single-thread performance. Wide decode (6+ instructions), large reorder buffers, aggressive prefetching. Used as the "prime" or "big" core in flagship mobile SoCs.
- Cortex-A series (A720, A725): Balanced performance and efficiency. Narrower decode (4 instructions), smaller structures. The "medium" core in big.LITTLE/DynamIQ configurations.
- Cortex-A series efficiency (A520, A525): Optimized for power efficiency. In-order or narrow out-of-order designs. The "little" core that handles background work.
Qualcomm's Snapdragon 8 Gen 3 uses a 1+5+2 configuration: one Cortex-X4 prime core at 3.3 GHz, five Cortex-A720 performance cores at 3.15 GHz, and two Cortex-A520 efficiency cores at 2.27 GHz. MediaTek's Dimensity 9300 went even more aggressive with an all-big-core design — no efficiency cores at all.
For a related perspective, see Power Semiconductor Devices: SiC MOSFETs, GaN HEMTs, and Wid.
Custom Core Designs
Apple
Apple's cores are the gold standard for ARM performance. They license the ARM instruction set architecture but design every microarchitectural detail in-house. Apple's cores are significantly wider than ARM's own Cortex designs — 8-wide decode, ROB exceeding 600 entries, and execution port configurations that ARM Ltd. doesn't offer. The performance gap between Apple's cores and ARM's reference designs has been roughly 30-50% in IPC for the last several generations.
Qualcomm
Qualcomm formerly designed fully custom cores (Kryo, Falkor) but returned to using modified ARM Cortex designs starting with Snapdragon 888. Their Oryon cores (Snapdragon X Elite for laptops) are a new custom design derived from the Nuvia acquisition — Nuvia was founded by ex-Apple chip architects, and Oryon shows that lineage with wider decode, larger caches, and stronger single-thread performance than standard Cortex designs.
NVIDIA
NVIDIA's Grace CPU uses ARM Neoverse V2 cores — ARM's data center core design. 72 cores with SVE2, targeting HPC and AI training workloads where it pairs with NVIDIA's own GPUs over NVLink-C2C. The Grace Hopper superchip combines a Grace CPU with an H100 GPU on a single module.
The ARM ecosystem's diversity is its strength. No single implementation approach dominates, and competition between licensees pushes performance forward faster than any one company could achieve alone.