Why Space Is Hard on Silicon
Chips in space face three problems that terrestrial electronics never worry about: radiation, extreme temperatures, and the impossibility of repair. A single energetic particle — a cosmic ray heavy ion or a trapped proton in the Van Allen belts — can flip a bit in memory, latch up a CMOS circuit, or permanently damage a transistor gate oxide. And you can't send a technician to swap the board.
The radiation environment varies dramatically depending on the orbit. Low Earth Orbit (LEO) satellites at 400-600 km altitude see total ionizing dose (TID) rates of maybe 5-10 krad per year behind typical shielding. Geostationary orbit (GEO) at 36,000 km is much worse — 10-50 krad per year. And anything passing through the South Atlantic Anomaly or the Van Allen belts gets hammered with proton fluxes that can cause hundreds of single-event effects per day.
Total Ionizing Dose and How It Kills Chips
TID is cumulative damage from ionizing radiation — mostly protons and electrons trapped in Earth's magnetic field, plus some gamma rays. When these particles pass through silicon dioxide (the gate oxide and isolation layers), they create electron-hole pairs. Electrons are mobile and get swept away, but holes get trapped in the oxide, building up positive charge over time.
This trapped charge shifts transistor threshold voltages. NMOS transistors see their Vt decrease — they start conducting at lower gate voltages, eventually becoming always-on. PMOS transistors see Vt increase in magnitude. The result is higher leakage current, slower switching, and eventually functional failure.
Radiation-hardened processes fight this by using different oxide materials, special transistor layouts, and sometimes silicon-on-insulator (SOI) substrates. BAE Systems' RH45 process, built on a 45nm SOI technology, can handle TID levels above 1 Mrad — that's enough for 15+ years in GEO orbit.
Single-Event Effects: When One Particle Ruins Your Day
Single-event upsets (SEUs) are the most common radiation effect in digital circuits. A heavy ion strikes a sensitive node — typically a storage element like an SRAM cell or a flip-flop — and deposits enough charge to flip the stored bit. The error rate depends on the particle flux and the critical charge of the node, which shrinks with each process generation.
We covered a related topic in Power Semiconductor Devices: SiC MOSFETs, GaN HEMTs, and Wid.
More dangerous are single-event latch-ups (SELs). A heavy ion can trigger the parasitic thyristor structure inherent in CMOS — the PNPN path between VDD and ground. Once latched, the circuit draws excessive current that can destroy the device in milliseconds if power isn't cut. This is why rad-hard designs often include current-sensing circuits that can power-cycle individual blocks within microseconds.
Single-event gate rupture (SEGR) and single-event burnout (SEB) are permanent destruction mechanisms, mainly affecting power MOSFETs and some memory cells. No amount of error correction helps here — the device is physically damaged.
Mitigation Approaches
Triple modular redundancy (TMR) is the classic defense against SEUs. You instantiate three copies of every logic block and vote on the output. If one copy gets upset, the other two outvote it. The cost is obvious: 3× the area and roughly 3× the power for the redundant logic, plus the voting circuits.
For memory, error-correcting codes (ECC) are standard. SECDED (single-error-correct, double-error-detect) Hamming codes handle the most common case of a single bit flip in a memory word. For higher reliability, BCH or Reed-Solomon codes can correct multiple bits, though they add latency and silicon area to the memory interface.
EDAC scrubbing — periodically reading and rewriting memory contents — prevents error accumulation. If an SEU flips a bit in a rarely-accessed memory location, it could sit there until a second hit creates a multi-bit error that overwhelms the ECC. Scrubbing catches these dormant errors before they compound.
See also: Việc Làm Bán Dẫn Việt Nam 2026: Lương & Tuyển Dụng.
Temperature Extremes and Their Effects
In space, a satellite's sun-facing side can reach +150°C while the shadow side drops to -150°C. Solar panels, thermal blankets, and heaters moderate the electronics environment, but even well-protected boards see temperature swings of -55°C to +125°C during orbital cycles. LEO satellites complete an orbit every 90 minutes, so the thermal cycling is relentless.
Standard commercial chips are rated to 0°C to +70°C or -40°C to +85°C for industrial grade. Military grade extends to -55°C to +125°C, which is the minimum for most space applications. But the qualification process is much more rigorous than the temperature range alone suggests — it includes thermal cycling endurance tests, burn-in at elevated temperature, and lot acceptance testing that samples every wafer lot.
The Rad-Hard Foundry Ecosystem
There's a surprisingly small number of foundries that produce radiation-hardened chips. The main players are:
- BAE Systems — their RH processes on 45nm and 12nm SOI are widely used for military and NASA missions
- Honeywell (now Qorvo) — produces ASIC platforms on 32nm SOI for rad-hard applications
- ST Microelectronics — offers rad-hard standard products and ASIC services, primarily from their Crolles fab
- Microchip Technology (via Microsemi acquisition) — FPGA and mixed-signal products qualified for space
One interesting trend is the use of commercial foundry processes with radiation-hardening-by-design (RHBD) techniques. Instead of using a specialized rad-hard process, you take a standard TSMC or GlobalFoundries node and apply layout techniques — guard rings, enclosed-gate transistors, redundant storage nodes — to achieve adequate radiation tolerance. This gets you access to newer, more capable processes at the cost of area overhead.
Xilinx's (now AMD's) Virtex-5QV FPGA took this approach, using a commercial 65nm process with RHBD techniques to achieve 1 Mrad TID tolerance and an SEU rate suitable for GEO missions. It gave space system designers access to a much more capable FPGA than any purpose-built rad-hard device could offer at the time.
Related reading: Foundry Business Model: How TSMC, Samsung, and Intel Foundry.
New Space and the COTS Approach
The New Space movement — SpaceX, Planet Labs, and their peers — has upended the traditional approach to space electronics. When you're launching constellations of hundreds or thousands of LEO satellites with design lifetimes of 3-5 years, paying $100,000 for a rad-hard processor doesn't make economic sense.
Instead, these companies use commercial off-the-shelf (COTS) components with system-level mitigation. The Raspberry Pi-class ARM processors in some CubeSats would horrify a traditional space systems engineer. But if you add watchdog timers, memory scrubbing in software, and design the satellite to gracefully reboot when something goes wrong, you can get acceptable reliability for short-mission LEO applications at a fraction of the cost.
It's a calculated bet. You'll have more anomalies per satellite, but when your constellation has 200 satellites and you can replace any one of them on the next launch, individual reliability matters less than fleet availability. The economics only work if the satellites are cheap enough to treat as somewhat expendable — which circles back to using cheap commercial chips.
Qualification and Testing
Space component qualification follows standards like MIL-PRF-38535 (for microcircuits) and ESA's ESCC specifications in Europe. The testing is extensive and expensive: heavy ion testing at cyclotron facilities (like Texas A&M's or Belgium's UCL), proton testing, TID testing with gamma sources (usually Cobalt-60), and destructive physical analysis (DPA) of sample units.
A full space qualification campaign for a new IC can cost $500K to $2M and take 12-18 months. That's before you've shipped a single flight unit. This cost structure is why the space semiconductor market, despite its high margins, represents less than 0.5% of the total semiconductor industry by revenue.