Semiconductor Lithography Beyond EUV
Extreme ultraviolet lithography was supposed to be the hard part. The industry spent over two decades and billions of dollars getting EUV into production. ASML's NXE:3400 and NXE:3600 scanners, operating at 13.5nm wavelength, finally made sub-7nm nodes commercially viable. But here's the thing: we're already bumping up against EUV's limits, and the question of what comes next is no longer theoretical.
Where EUV Stands Today
As of 2026, ASML's latest production scanner is the NXE:3800E, with a numerical aperture (NA) of 0.33 and a throughput of roughly 200 wafers per hour at 30mJ/cm2 dose. TSMC uses EUV extensively at its N3 and N2 nodes. Samsung's SF2 (2nm) node uses EUV for critical metal layers. Intel's 18A process uses EUV with some layers requiring double patterning.
The resolution limit of 0.33NA EUV is around 13nm half-pitch for single patterning. For anything tighter — and we're definitely going tighter — you need either multi-patterning with current EUV or a higher-NA system.
High-NA EUV: The Next Step That's Already Here
ASML's EXE:5000 (originally called the TWINSCAN EXE platform) uses a 0.55NA optic, which should resolve features down to about 8nm half-pitch in a single exposure. Intel received the first EXE:5000 at its Hillsboro fab in late 2024 and has been running qualification wafers since early 2025. TSMC ordered multiple units for its Arizona fab.
But High-NA EUV comes with problems that I think the industry is only beginning to appreciate:
- The field size is halved. The 0.33NA scanners expose a 26mm x 33mm field. The 0.55NA system exposes roughly 26mm x 16.5mm. This means you need stitching for large dies, or your max die size shrinks. For GPU designs that already push reticle limits, this is a serious constraint.
- The anamorphic optics use 4x demagnification in one axis and 8x in the other, which complicates mask design and introduces directional resolution differences.
- Throughput. Early reports suggest the EXE:5000 runs at about 80-100 wafers per hour, less than half of the mature 0.33NA tools. At $350-400 million per tool, that's a huge cost-per-wafer-pass increase.
- Resist sensitivity. You need new resist chemistries (metal-oxide resists, specifically tin-oxide based materials from companies like Inpria, now owned by JSR) that can achieve the line-edge roughness specifications at lower doses. Chemically amplified resists don't cut it anymore at these dimensions.
The Resist Problem Is Bigger Than You Think
I'd argue that resist technology is now the primary bottleneck, more than the scanner itself. At 8nm half-pitch, you're placing features with just a few dozen photons per pixel. The statistical variation in photon absorption — the shot noise problem — directly translates to line-edge roughness (LER) and line-width roughness (LWR). Current EUV resists achieve about 2.5-3nm LER (3-sigma). For 8nm half-pitch, you need sub-1.5nm LER, ideally below 1nm.
We covered a related topic in Đóng Gói Chip Tiên Tiến 2026: CoWoS, Chiplet, FOPLP.
Metal-oxide resists from Inpria/JSR and similar materials from TOK, Shin-Etsu, and others absorb EUV photons more efficiently than traditional polymer-based chemically amplified resists. Their absorption cross-section at 13.5nm is substantially higher due to the tin atoms. But they bring their own challenges: defectivity, etch selectivity, and integration into existing fab process flows.
Beyond High-NA: What Are the Real Options?
When people ask "what comes after EUV?", they usually expect a single answer. In reality, there are multiple candidates, and I think most of them are further from production than their advocates suggest.
Hyper-NA EUV (NA > 0.55): ASML has studied 0.75NA systems. The physics works, but the engineering is brutal. The mirror coatings would need to work at steeper angles, the field size shrinks further, and the pellicle challenge becomes even harder. I don't think we'll see a 0.75NA tool before 2032 at the earliest, if ever. The cost/benefit math might not close.
Multi-beam electron-beam lithography: Companies like IMS Nanofabrication (now an Applied Materials subsidiary) have been working on massively parallel e-beam systems. Their MBMW-101 uses 262,144 individually controllable electron beams to write patterns directly, no mask needed. Throughput has been the historical killer for e-beam — it's orders of magnitude slower than optical projection. Current multi-beam systems achieve maybe 5-10 wafers per hour for critical layers. That's too slow for high-volume manufacturing, but it's finding use in mask writing and specialty applications.
Directed self-assembly (DSA): Block copolymers that naturally phase-separate into periodic nanostructures at pitches below 20nm. IBM and IMEC have done extensive work here. The idea is you use a coarser lithography step to create a guide pattern, then let the polymer do the fine patterning. The challenge is defectivity — every missing or misplaced domain is a killer defect. Defect densities need to be below 0.01/cm2 for production, and current DSA processes are still orders of magnitude above that.
For a related perspective, see ARM Architecture Evolution: From ARMv8 to ARMv9 and Custom C.
Nanoimprint lithography (NIL): Canon's nanoimprint tools physically stamp a pattern onto the wafer using a 1:1 template. Resolution can be extraordinary — sub-5nm features have been demonstrated. SK Hynix has been evaluating NIL for NAND flash patterning, and there's genuine interest for memory applications where you have highly repetitive patterns. Overlay accuracy and template defectivity are the main hurdles. For logic, where every layer has a different pattern, the need for unique templates per design per layer makes it impractical.
Next-generation wavelengths: There have been proposals for "beyond EUV" using even shorter wavelengths — say 6.x nm (sometimes called BEUV). The physics is challenging because there are almost no materials with good reflectivity at those wavelengths. The entire EUV optical train depends on Mo/Si multilayer mirrors with ~70% reflectivity per bounce. At 6.x nm, you'd need entirely new mirror materials, and absorption in any residual gas becomes a nightmare. I honestly think this is a dead end for the foreseeable future.
The Practical Path Forward
Here's my honest assessment of where the industry is heading through 2030:
- 0.33NA EUV with double/triple patterning continues for N2 and A14 (Intel 14A) nodes. It works, the tools are mature, and fabs already own hundreds of them.
- 0.55NA (High-NA) EUV enters production around 2027-2028 for the most critical layers at sub-2nm nodes. It'll replace some multi-patterning EUV steps, which actually saves money despite the higher tool cost.
- Complementary techniques — self-aligned processes, atomic layer deposition for edge placement, and selective deposition — do as much of the heavy lifting as the scanner. The scanner is only half the story; the process integration is the other half.
- DSA and NIL remain niche for the next five years. They'll find homes in specific applications (memory, photonics) but won't replace projection lithography for leading-edge logic.
Computational Lithography: The Unsung Hero
Something I think deserves much more attention is computational lithography — specifically inverse lithography technology (ILT). Traditional optical proximity correction (OPC) starts with the desired pattern and iteratively adjusts the mask to compensate for optical distortion. ILT flips this around: given the desired wafer pattern and a physics model of the scanner, it computes the mathematically optimal mask shape. The resulting masks look nothing like the target circuit pattern — they're filled with curvilinear features that no human would design, but they produce sharper images on the wafer.
Synopsys, Siemens EDA, and ASML's Brion subsidiary all offer ILT solutions. The computation is enormous — a single mask layer for a modern SoC can take tens of thousands of GPU-hours to optimize. NVIDIA has actually partnered with ASML to accelerate this using their cuLitho library, which runs the optical simulations on H100 GPUs. TSMC reported a 40x speedup using cuLitho for computational lithography at N2. When people talk about AI helping semiconductor manufacturing, this is one place where it's already delivering real results.
This connects to the ideas in GAA vs FinFET: So Sánh Kiến Trúc Transistor Chi Tiết 2026.
Multi-beam mask writers from IMS Nanofabrication can actually write these curvilinear masks efficiently, since electron beams don't care about Manhattan geometries the way traditional laser mask writers do. That's a key enabler — you can't use ILT-optimized curvilinear masks if your mask writer can only produce rectilinear shapes.
The Economics of Advanced Lithography
Let's talk money, because economics ultimately determines adoption. An ASML NXE:3800E costs roughly $200 million. The EXE:5000 High-NA tool is estimated at $350-400 million. A leading-edge fab needs 10-15 EUV scanners for high-volume production of a single process node. That's $2-4 billion in scanners alone, before you count the rest of the fab equipment.
Mask costs are another factor. A full mask set for a 3nm logic design runs $20-30 million. With EUV, some masks require near-zero defectivity — any particle larger than about 50nm on the mask pattern area is a printable defect at 4x demagnification. Pellicles (thin membranes protecting the mask surface) for EUV have been a persistent challenge; they need to transmit >90% of EUV light while being mechanically stable. ASML, Mitsui, and IMEC have all worked on EUV pellicles using materials like polysilicon, carbon nanotubes, and ruthenium-capped membranes.
The reality is that lithography progress isn't going to come from a single magic tool anymore. It's a combination of better scanners, better resists, better process integration, and better computational lithography. That's less exciting than announcing a new wavelength, but it's how the industry actually moves forward.