Optical Interconnects for Data Center Chips
Copper traces are running out of steam. That's not a controversial opinion anymore — it's the consensus among anyone who's tried to push 112 Gbps PAM4 signaling across a 2-meter cable in a hot data center aisle. The power required to drive electrical signals at those rates is becoming absurd, and we're already looking at 224 Gbps per lane for the next generation. Optical interconnects aren't a futuristic concept; they're shipping today, and the real question is how far toward the chip they'll eventually reach.
Why Copper Hits a Wall
Electrical signaling suffers from frequency-dependent loss. A copper trace on FR4 PCB material loses roughly 1 dB per inch at 28 GHz. At 56 GHz — the Nyquist frequency for 112G PAM4 — you're looking at nearly 2 dB per inch. For a 10-inch trace on a backplane, that's 20 dB of channel loss before you even account for connectors, vias, and crosstalk. The equalization circuitry to recover a signal through that kind of channel eats power. I've seen SerDes blocks consuming over 15 pJ/bit at 112G, and that number only goes up as data rates climb.
Meanwhile, optical fiber doesn't care about frequency in the same way. A single-mode fiber can carry signals hundreds of meters with negligible loss at data center wavelengths (around 1310 nm). Multimode fiber works well for shorter reaches up to about 100 meters. The energy cost shifts from the channel to the transceivers at each end, and those are getting cheaper and more efficient every generation.
Where the Industry Stands Right Now
Most data centers today use pluggable optical transceivers — the QSFP-DD and OSFP form factors are standard for 400G and 800G links. Companies like Coherent (formerly II-VI and Finisar), Broadcom, Intel, and Marvell supply these modules. A typical 800G OSFP module uses eight lanes at 100G each, with EML (electro-absorption modulated laser) or silicon photonics transmitters.
But the pluggable model has its own issues:
This connects to the ideas in Chip Ô Tô Tự Lái 2026: Tesla vs Qualcomm vs Mobileye.
- Each transceiver consumes 15-25W for an 800G module, and a switch with 51.2 Tbps capacity needs 64 of them
- The electrical path from the switch ASIC to the front panel faceplate still runs through lossy copper, requiring retimer chips that add latency and power
- Front panel density is maxed out — you can only physically fit so many OSFP cages
This is pushing the industry toward co-packaged optics (CPO) and near-package optics (NPO), where the optical engine sits right next to the switch ASIC instead of on the front panel.
Co-Packaged Optics: The Promise and the Challenges
CPO puts the optical engine on the same substrate as the switch chip, sometimes inside the same package. Broadcom demonstrated this with their Memory Tomahawk 5 platform, and Marvell has shown CPO prototypes using their silicon photonics technology. The idea is simple: by eliminating the long copper traces to the faceplate, you remove the need for power-hungry retimers and reduce SerDes power dramatically.
In theory, CPO can cut interconnect power by 30-50%. In practice, there are real engineering headaches:
- Fiber management becomes complicated — instead of plugging cables into the front panel, you've got fiber pigtails coming directly off the package, which can't be field-replaced easily
- Thermal coupling between the ASIC (which might dissipate 500W+) and the optical components (which are temperature-sensitive) creates reliability concerns
- Testing and repair workflows change completely — a bad optical engine could mean scrapping the entire expensive package
- The supply chain has to coordinate between the switch ASIC vendor and the photonics vendor in new ways
I think the industry will eventually get past these issues, but it's going to take longer than the optimists predict. My guess is CPO becomes mainstream for hyperscaler switches by 2027-2028, while enterprise data centers continue with pluggable optics for another 5+ years after that.
See also: HBM4 Memory Technology: Architecture, Bandwidth, and the AI .
Silicon Photonics vs. III-V Materials
There's an ongoing debate about the right material platform for optical interconnects. Silicon photonics — pioneered by Luxtera (now Cisco), Intel, and GlobalFoundries — builds optical components in a standard silicon process. The advantage is using existing CMOS fabs and integrating photonics with electronics on the same wafer. Intel's been shipping silicon photonics transceivers for years, and their process runs on 300mm wafers at their fab in New Mexico.
The downside? Silicon is an indirect bandgap material, which means it can't efficiently emit light. You still need a III-V laser (typically indium phosphide) bonded or coupled to the silicon chip. This hybrid integration adds cost and complexity.
Companies like Coherent and Lumentum use native III-V platforms (InP) for their transmitters, which are naturally good at generating and modulating light. The tradeoff is that InP wafers are smaller (typically 100mm or 150mm) and the fabrication process is less mature than silicon CMOS.
Honestly, I'd argue both approaches will coexist. Silicon photonics wins when you need high integration density and want to take advantage of CMOS manufacturing scale. III-V wins when raw optical performance matters more than integration. For data center interconnects specifically, silicon photonics seems to be pulling ahead thanks to the manufacturing economics.
See also: Semiconductor Industry Cycles: Boom, Bust, and Demand Foreca.
Linear-Drive Optics and DSP-Free Architectures
One of the most interesting recent developments is the push toward linear-drive (or DSP-free) optics. Traditional optical transceivers include a digital signal processor (DSP) chip that handles encoding, equalization, and forward error correction. These DSPs consume significant power — sometimes half the module's total power budget.
Linear-drive optics eliminate the DSP by using a clean enough optical channel that the signal doesn't need digital recovery. The switch ASIC's SerDes drives the optical modulator directly (or through a simple linear amplifier). This approach, championed by companies like Ayar Labs and some hyperscalers, can reduce per-link power to under 5 pJ/bit.
The catch is that linear-drive requires very low-loss optical channels and tight specifications on the components. It works best for short reaches (a few meters to tens of meters) within a rack or between nearby racks, which is exactly where CPO operates.
What's Coming Next
Looking further out, there are even more ambitious optical interconnect concepts in development:
- Ayar Labs is working on in-package optical I/O chiplets that connect directly to the processor die using UCIe or similar die-to-die interfaces. They've demonstrated a chip that converts electrical signals to optical at the package level, using micro-ring resonator modulators on a silicon photonics platform.
- Lightmatter is building photonic interconnect fabric for AI compute clusters, using their Passage platform to connect chips optically within a single system. Their claim is wafer-scale connectivity without the power overhead of electrical mesh networks.
- Intel's integrated photonics research group has demonstrated monolithically integrated lasers on silicon — if they can bring this to production, it would eliminate the III-V bonding step entirely.
The long-term vision that many researchers share is optical signals reaching all the way to the processor die itself — replacing the metal interconnects between chiplets in a multi-die package. That's probably 10-15 years out, but the building blocks are being proven in labs today.
For anyone designing data center infrastructure today, I'd recommend planning for 800G pluggable optics as the near-term standard, with an architecture that can accommodate CPO when it matures. The transition won't happen overnight, and the coexistence period will be long. But the direction is unmistakable — photons will replace electrons for more and more of the data path inside our data centers.