Chiplet Architecture
The Multi-Die Future of Processors

Why Chiplets? The End of Monolithic Scaling

For decades, semiconductor advancement followed a predictable pattern: shrink transistors, pack more onto a single die, increase performance. A single monolithic chip contained everything — CPU cores, cache, memory controllers, I/O interfaces — manufactured together on one slab of silicon. This approach worked brilliantly when die sizes stayed below 300mm² and process yields remained high.

By the early 2020s, that model began to break. High-performance server processors demanded 50+ billion transistors, pushing monolithic die sizes past 800mm². At advanced nodes like 5nm and 3nm, manufacturing a single die that large becomes economically devastating: defect density means only 20-35% of dies on a wafer function correctly. Each scrapped die wastes expensive leading-edge silicon.

The physics and economics problem

Three forces converged to make chiplets inevitable:

• Yield wall: Defect density on a wafer is roughly constant per unit area. Doubling die size more than doubles the probability that at least one defect lands on the die. A 100mm² die at 0.1 defects/cm² yields ~90%; a 600mm² die at the same defect rate yields ~55%.
• Cost wall: Leading-edge wafers cost $16,000-20,000 at 3nm. When 45-65% of large dies are discarded, the effective cost per working die can exceed $500. Splitting that design into four chiplets at 80% yield each dramatically reduces waste.
• Reticle limit: The maximum die size is constrained by the lithography reticle — approximately 858mm² (26mm x 33mm). No monolithic chip can exceed this physical limit, yet demand for transistor counts continues to grow.

Chiplet vs Monolithic: Architecture Comparison

The fundamental difference between chiplet and monolithic design lies in how silicon functionality is partitioned and connected. Understanding the trade-offs reveals why neither approach universally dominates.

Monolithic design retains clear advantages in latency-sensitive, small-die applications. Smartphone SoCs like Apple's A-series and Qualcomm's Snapdragon remain monolithic because their die sizes (100-150mm²) don't trigger severe yield problems, and the on-die bandwidth between CPU, GPU, and NPU blocks is critical for performance. Chiplets become advantageous once the equivalent monolithic die exceeds roughly 300mm², which is precisely the territory of server CPUs, HPC processors, and AI accelerators.

The UCIe Standard: Universal Chiplet Interconnect Express

Before UCIe, every chiplet-based processor used proprietary die-to-die interconnects. AMD's Infinity Fabric, Intel's EMIB links, and TSMC's chip-on-wafer interfaces were all incompatible. UCIe changes this by defining an open standard for chiplet communication — the "USB of chiplets."

UCIe specification overview

UCIe defines three layers: the physical layer (electrical signaling and bump pitch), the die-to-die adapter layer (link training, error correction), and the protocol layer (supporting CXL, PCIe, and streaming protocols). UCIe 2.0, ratified in 2025, delivers significant improvements over the original specification:

The consortium behind UCIe includes AMD, Intel, Arm, TSMC, Samsung, Google, Meta, Microsoft, Qualcomm, and ASE — essentially the entire semiconductor ecosystem. This breadth of support signals that UCIe will become the de facto standard for multi-vendor chiplet integration, much as PCIe standardized I/O interconnects decades ago.

AMD's Chiplet Strategy: EPYC and Ryzen

AMD pioneered commercial chiplet architecture with the first-generation EPYC "Naples" processor in 2017, and has iterated aggressively ever since. AMD's approach is the industry's most mature chiplet implementation and provides the clearest demonstration of chiplet economics.

EPYC server processor evolution

AMD's EPYC lineup splits processor functionality between compute chiplets (CCDs, each containing CPU cores and L3 cache) and a central I/O die (IOD) handling memory controllers, PCIe lanes, and inter-die communication via Infinity Fabric.

The key insight in AMD's architecture is the separation of compute and I/O. Compute chiplets (CCDs) use the most advanced process node available — currently TSMC 3nm for Turin — because transistor density directly translates to core count and cache capacity. The I/O die (IOD) remains on a mature node (6nm) because analog circuits like SerDes, PHYs, and memory controllers don't benefit significantly from leading-edge scaling but do benefit from mature, high-yield manufacturing.

Ryzen consumer chiplets and 3D V-Cache

AMD extends its chiplet strategy to consumer desktop with Ryzen processors, notably introducing 3D V-Cache — TSMC's SoIC 3D stacking technology that bonds an additional 64MB SRAM cache die directly on top of the CCD. The Ryzen 9 9950X3D combines two CCDs (one with 3D V-Cache), delivering 144MB of total L3 cache. This hybrid approach — chiplets for modularity, 3D stacking for performance — demonstrates how packaging technologies compound.

Intel's Tile Architecture: Foveros, EMIB, and Disaggregated Design

Intel uses the term "tiles" rather than chiplets, but the concept is the same: decomposing a processor into multiple specialized dies interconnected via advanced packaging. Intel's approach differs from AMD's in its aggressive use of 3D stacking (Foveros) alongside 2.5D interconnects (EMIB).

Meteor Lake and beyond: client tiles

Intel's Meteor Lake (2023) was the company's first client processor using a tile architecture, combining four separate tiles on a Foveros base die: a compute tile (Intel 4), a graphics tile (TSMC N5), a SoC tile (TSMC N6), and an I/O tile (TSMC N6). This demonstrated a radical concept: Intel manufacturing some tiles internally while outsourcing others to TSMC, selecting the optimal foundry and process node for each function.

The Panther Lake generation (2026) refines this approach with Intel 18A compute tiles, delivering improved performance and power efficiency while maintaining the multi-foundry, multi-node tile strategy.

Ponte Vecchio and GPU tiles

Intel's most extreme chiplet implementation was the Ponte Vecchio GPU for HPC, which combined 47 individual tiles across multiple packaging technologies:

• 16 compute tiles (Xe-HPC cores) on Intel 7 process
• 8 Rambo cache tiles providing 408MB of L2 cache
• 8 HBM2E stacks providing 128GB memory at 3.2 TB/s bandwidth
• 2 base tiles connecting everything via EMIB and Foveros
• 11 EMIB connections and 2 Foveros bonds in a single package

While Ponte Vecchio faced yield and software challenges, it proved that complex multi-die GPU architectures are feasible — a lesson Intel and NVIDIA are both applying to next-generation AI accelerators.

Advanced Packaging Technologies

Chiplets are only as good as the packaging that connects them. Advanced packaging is now the critical enabler — and the primary capacity bottleneck — in the semiconductor industry.

2.5D packaging: side-by-side interconnection

In 2.5D packaging, chiplets sit side-by-side on an interposer or redistribution layer that provides high-density wiring between dies.

• TSMC CoWoS (Chip on Wafer on Substrate): The dominant 2.5D platform, used in NVIDIA H100/H200/B200, AMD MI300X, and Google TPU v5. A silicon interposer provides thousands of die-to-die connections at 45-55 μm bump pitch. CoWoS-S uses a silicon interposer; CoWoS-L uses a hybrid with local silicon interconnect bridges (LSI) embedded in organic substrate, enabling larger package sizes for AI accelerators.
• Intel EMIB (Embedded Multi-die Interconnect Bridge): A small silicon bridge die embedded in the organic substrate at the boundary between two tiles. More cost-effective than a full interposer but limited to die-edge connections.

3D packaging: vertical stacking

3D packaging stacks chiplets vertically using through-silicon vias (TSVs), achieving much higher interconnect density than 2.5D approaches.

• Intel Foveros: Face-to-face bonding of a top die to a bottom base die via microbumps (36-50 μm pitch). Foveros Direct advances this to hybrid bonding at sub-10 μm pitch, eliminating solder bumps for direct copper-to-copper connections.
• TSMC SoIC (System on Integrated Chips): TSMC's 3D stacking technology using hybrid bonding (sub-1 μm pitch). SoIC enables AMD's 3D V-Cache and is the foundation for future 3D chiplet integration at densities approaching monolithic on-die interconnects.
• Samsung X-Cube: Samsung's 3D stacking technology using TSV and hybrid bonding, targeting high-bandwidth memory and logic integration.

Heterogeneous Integration: Mixing Process Nodes

One of chiplet architecture's most powerful advantages is heterogeneous integration — manufacturing each chiplet on the process node best suited to its function, then assembling them into a single package.

Not every circuit benefits equally from process scaling. Digital logic (CPU cores, GPU shaders, AI accelerators) benefits enormously from smaller transistors: more transistors, higher frequency, lower power. But analog circuits — SerDes transceivers, memory PHYs, power management, RF blocks — often perform worse on leading-edge nodes due to voltage headroom constraints, noise characteristics, and design rule complexity.

Real-world heterogeneous designs

• AMD EPYC Turin: 3nm compute chiplets (CCDs) paired with a 6nm I/O die (IOD). The CCDs need cutting-edge density for cores and cache; the IOD uses mature 6nm for reliable memory controllers and PCIe 5.0 PHYs.
• Intel Meteor Lake: Intel 4 compute tile, TSMC N5 graphics tile, TSMC N6 SoC and I/O tiles. Intel uses its own fabs for compute while outsourcing GPU and peripheral tiles to TSMC.
• AMD MI300A APU: TSMC N5 compute dies (CDNA 3 GPU + Zen 4 CPU), TSMC N6 I/O die, and HBM3 stacks — combining three different silicon technologies in one package for HPC workloads.

This mix-and-match approach means a chiplet-based design can use the most expensive leading-edge node only where it matters most (compute), while keeping high-volume I/O and analog functions on cheaper, higher-yield mature nodes. The economic impact is substantial: only 30-40% of total silicon area needs leading-edge manufacturing, compared to 100% in a monolithic design.

Cost and Yield Advantages

The economic case for chiplets is compelling and quantifiable. Consider a hypothetical 600mm² server processor design at TSMC 3nm.

Monolithic vs chiplet yield analysis

Assuming a defect density of 0.09 defects/cm² (typical for a mature 3nm process):

• Monolithic 600mm² die: Using the negative binomial yield model, expected yield is approximately 38%. From a 300mm wafer producing ~74 gross dies, only ~28 are functional. At $18,000 per wafer, that's roughly $643 per good die.
• Four 150mm² chiplets: Each chiplet yields approximately 78%. From ~304 gross chiplets per wafer, ~237 are functional. Cost per good chiplet is approximately $76. Four chiplets total ~$304 in silicon cost — even before accounting for the I/O die and packaging.

Even adding $80-120 for advanced packaging (CoWoS interposer, assembly, testing), the chiplet approach saves $200-300 per processor compared to monolithic — a 30-45% reduction in silicon cost. At production volumes of millions of units, this translates to hundreds of millions of dollars in savings.

Product portfolio leverage

Beyond yield, chiplets enable a second cost advantage: product segmentation from common building blocks. AMD produces a single CCD design, then assembles different products by varying the chiplet count:

• Ryzen 5: 1 CCD (6-8 cores) — mainstream desktop
• Ryzen 9: 2 CCDs (16 cores) — enthusiast desktop
• EPYC (entry): 4 CCDs (32 cores) — entry server
• EPYC (max): 16 CCDs (128 cores) — high-end server

One CCD tape-out — one mask set, one validation effort — serves the entire product stack. In monolithic design, each segment would require its own die, multiplying engineering and mask costs ($300-500M per tape-out at advanced nodes).

The Chiplet Ecosystem: 2027 and Beyond

Near-term developments (2027)

• UCIe 2.0 silicon shipping: First products with UCIe 2.0 compliant die-to-die interfaces at 10 μm bump pitch, doubling bandwidth density over current implementations while halving per-bit energy.
• 3D chiplet stacking at scale: TSMC SoIC and Intel Foveros Direct enable logic-on-logic 3D stacking with hybrid bonding at sub-1 μm pitch, approaching on-die interconnect density. This unlocks vertically integrated compute-plus-cache architectures beyond AMD's current 3D V-Cache.
• AI accelerator chiplets: NVIDIA's next-generation GPU architecture post-Blackwell is expected to use 3-4 compute chiplets per GPU, with each die manufactured on TSMC N2. Die-to-die bandwidth will need to exceed 20 TB/s to avoid becoming a bottleneck for transformer model training.
• Optical die-to-die interconnects: Companies like Ayar Labs are developing silicon photonic chiplets that replace electrical die-to-die links with optical connections, offering 10x bandwidth-per-watt improvement. Early integration into multi-die packages is expected by 2027-2028.

The multi-vendor chiplet marketplace

The ultimate vision for chiplets — articulated by UCIe proponents and DARPA's CHIPS program — is a marketplace where companies can purchase pre-validated chiplets from different vendors and assemble custom processors. A startup might combine a licensed Arm compute chiplet, a custom AI accelerator chiplet, and an off-the-shelf I/O chiplet into a domain-specific processor without designing any silicon from scratch.

This vision remains 3-5 years away from broad commercial reality. The technical standards (UCIe) are converging, but the ecosystem requires solved problems in: cross-vendor thermal modeling, standardized KGD testing protocols, shared PDK interfaces for packaging, and system-level software abstraction layers. The trajectory, however, is clear — chiplets are not a transitional technology but the permanent future of high-performance processor design.

Frequently Asked Questions

Conclusion

Chiplet architecture has transitioned from an innovative alternative to the default approach for high-performance processor design. The economics are unambiguous: at advanced process nodes, splitting large designs into multiple smaller dies delivers higher yields, lower costs, faster time-to-market, and the flexibility to mix process nodes — advantages that compound as transistor scaling makes leading-edge manufacturing increasingly expensive.

The UCIe standard is laying the groundwork for an interoperable chiplet ecosystem, while packaging technologies like TSMC CoWoS, Intel Foveros, and 3D hybrid bonding provide the physical interconnect fabric. As these technologies mature and 2nm manufacturing pushes monolithic yield challenges further, chiplets will extend from servers and AI accelerators into networking, automotive, and eventually high-end consumer devices. The monolithic era isn't ending — but for silicon at the frontier of performance, the future is unmistakably multi-die.