The Metric That Actually Determines Chip Cost
Node size gets all the headlines. "TSMC announces 2nm" makes the news. But inside every fab, the number that engineering teams obsess over is yield — the percentage of functional dies per wafer. A perfect process on a theoretically superior node that yields 30% is commercially useless compared to a mature process at a larger node yielding 90%.
Here's the basic math. A 300mm wafer costs roughly the same to process regardless of what you're making on it — somewhere between $3,000 and $16,000 depending on the node and number of mask layers. If your die is 100mm² and the wafer yields 500 good dies at 95% yield, your cost per die is about $32. Drop that yield to 50%, and it's $64. For a large GPU die at 800mm² where you only get about 60 dies per wafer, the yield sensitivity is even more brutal.
Where Defects Come From
Defects fall into two broad categories: random and systematic.
Random Defects
Particles, contamination, and stochastic variation in the manufacturing process cause random defects distributed unpredictably across the wafer. The classic model for estimating yield from random defects is the Poisson model: Y = e^(-D₀ × A), where D₀ is defect density per cm² and A is die area. More commonly, fabs use the negative binomial model which accounts for defect clustering — defects aren't perfectly random, they tend to clump.
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Defect density for a mature process at TSMC or Samsung runs around 0.05-0.1 defects/cm². At process introduction, it might be 0.5-1.0 defects/cm² or higher. Getting from initial "risk production" to high-volume manufacturing is essentially the story of driving D₀ down through thousands of incremental improvements.
Systematic Defects
These come from design-process interactions: certain layout patterns that don't print well, metal fills that cause stress, via configurations with reliability issues. Design-for-manufacturability (DFM) rules try to prevent these, but they're never perfect. Lithography hotspots — places where the pattern is near the resolution limit of the exposure system — are a common source.
Yield Learning Curves
Every new process node follows an S-curve for yield improvement. The first wafers off a new node might yield 20-30%. Over 12-18 months of continuous improvement, the yield climbs toward 80-90%. TSMC's N3 (3nm) reportedly took about 12 months to ramp from risk production yields to volume-ready yields above 70%.
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The learning rate depends heavily on how different the new node is from the previous one. Shrinks that reuse most of the process flow (like TSMC's N7 to N6) ramp much faster than nodes introducing new transistor architectures (like the transition from FinFET to GAA nanosheet at 3nm/2nm).
Excursion Management
A yield "excursion" is when something goes wrong and yield drops suddenly. Maybe a chemical bath drifted out of spec, or a piece of equipment introduced particles. Catching these fast is critical. Modern fabs run statistical process control (SPC) on hundreds of parameters at every step, with automated disposition systems that can quarantine wafers before they accumulate more processing cost.
Yield Enhancement Techniques
Redundancy is the oldest trick. Memory chips have had spare rows and columns for decades — blow a fuse during test to redirect from a defective row to a spare. Modern SRAM arrays use similar techniques. For logic chips, redundancy is harder, but some designs include redundant cores or functional blocks that can be disabled if defective.
See also: Interconnect Scaling: Why On-Chip Wiring Is the New Bottlene.
Binning is another yield play. Not every die performs identically even if they all function. Faster dies get sold as the premium SKU, slower ones as the budget part. NVIDIA and AMD have used this for years — a GPU die with one disabled streaming multiprocessor might ship as a lower-tier product rather than being scrapped. Intel's been doing it since the Pentium days.
Chiplet Architectures and Yield
This is where chiplets really shine. AMD's move to chiplets with Zen 2 wasn't just about mixing nodes — it was a yield play. Instead of one enormous monolithic die at 300mm², they could build multiple smaller compute chiplets at ~80mm² each. The yield math is exponential: halving the die area more than doubles the yield for a given defect density. A defect that would have killed a 300mm² monolithic die only kills one small chiplet, which can be discarded while the rest are still good.
The Economics of Mature Nodes
There's a reason the semiconductor industry still produces massive volumes at 28nm, 40nm, and 65nm. These nodes have been running for over a decade. Their defect densities are incredibly low, their yields approach 99%, and the equipment is fully depreciated. The cost per transistor at these nodes isn't the lowest — that prize goes to the latest leading edge — but the cost per functional die is dirt cheap.
I'd argue that yield engineering is the most underappreciated discipline in semiconductors. The physics of shrinking transistors gets the attention, but it's the yield engineers who actually make it profitable to manufacture chips at the bleeding edge.