It All Starts with Sand — Sort Of
Every chip begins as a lump of polycrystalline silicon, which itself came from quartzite sand refined to 99.9999999% purity (that's nine nines). The Siemens process or fluidized bed reactor converts metallurgical-grade silicon into electronic-grade polysilicon, and from there, the Czochralski method pulls a single-crystal ingot — a cylindrical boule weighing up to 200 kg for 300mm production.
The ingot gets sliced into wafers about 775 µm thick using diamond wire saws. After lapping, etching, and chemical-mechanical polishing (CMP), you end up with mirror-finish wafers ready for the fab. Each wafer will eventually hold hundreds or thousands of individual dies.
Front-End-of-Line: Building the Transistors
FEOL is where the actual transistors get made. The process repeats a cycle of deposition, lithography, and etching — sometimes hundreds of times for a modern chip.
Oxidation and Film Deposition
The wafer first gets a thin gate oxide layer, grown in a furnace at around 800-1000°C. For advanced nodes (sub-7nm), this isn't plain silicon dioxide anymore — it's a high-k dielectric like hafnium oxide (HfO₂) that lets you maintain gate control with a physically thicker layer. Chemical vapor deposition (CVD) and atomic layer deposition (ALD) handle most film depositions. ALD is particularly critical at advanced nodes because it deposits material literally one atomic layer at a time, giving you angstrom-level thickness control.
Related reading: Sensor Chip Design: CMOS Image Sensors, LiDAR Receivers, and.
Lithography: Printing the Pattern
This is the most expensive single step. A photomask carrying the circuit pattern gets projected onto the wafer through a reduction lens (typically 4:1). For nodes at 7nm and below, extreme ultraviolet (EUV) lithography at 13.5nm wavelength replaced the multi-patterning workarounds that 193nm immersion lithography needed. ASML's TWINSCAN NXE:3600 can expose over 160 wafers per hour. The photoresist — a light-sensitive polymer — gets chemically altered where the light hits, and a developer solution washes away either the exposed or unexposed regions depending on whether you're using positive or negative resist.
Etching
Dry plasma etching (reactive ion etching, or RIE) removes material where the resist was cleared. The selectivity between materials matters enormously — you need to etch silicon without destroying the oxide underneath. For 3D structures like FinFETs and gate-all-around (GAA) transistors, the etch profiles get incredibly complex. High-aspect-ratio etches for 3D NAND can have aspect ratios exceeding 60:1.
Ion Implantation and Annealing
Doping introduces controlled impurities (boron for p-type, phosphorus or arsenic for n-type) into specific regions of the silicon. An ion implanter accelerates these atoms to energies between 1 keV and several MeV, embedding them at precise depths. Rapid thermal annealing (RTA) at temperatures around 1000°C for a few seconds activates the dopants and repairs crystal damage from the implant.
We covered a related topic in Clean Room Technology: Contamination Control in Semiconducto.
Back-End-of-Line: Wiring It All Together
BEOL connects the billions of transistors using metal interconnects. Modern chips have 12-15 metal layers, starting with the thinnest local wires at the bottom and progressively thicker global wires at the top.
The dual-damascene process is standard: you etch trenches and vias into a low-k dielectric, deposit a barrier metal (tantalum/tantalum nitride), fill with copper using electroplating, then polish back the excess with CMP. At advanced nodes, the copper resistance in the thinnest wires becomes a real problem — the wire width approaches copper's mean free path (~39nm at room temperature), causing resistivity to spike. That's why there's active research into ruthenium and molybdenum as potential replacements for the lowest metal layers.
Wafer Testing, Dicing, and Packaging
Before the wafer leaves the fab, every die gets a preliminary electrical test (wafer probe) using a probe card with thousands of tiny needles. Dies that fail get ink-marked. The wafer then goes to dicing — a diamond saw or laser cuts it into individual chips.
See also: Verification and Testing: How Billion-Transistor Chips Get V.
Packaging is its own discipline. The bare die gets attached to a substrate, wire-bonded or flip-chip connected, encapsulated in epoxy molding compound, and tested again. For high-performance chips, advanced packaging like TSMC's CoWoS or Intel's EMIB provides much higher interconnect density than traditional packaging.
The Numbers That Matter
A modern 300mm fab costs $15-20 billion to build and takes 2-3 years before it's producing at volume. A single EUV lithography tool costs around $200 million. The entire process from bare wafer to tested die takes 2-3 months and involves 500-1000 individual processing steps. And here's what's wild — a single particle of dust larger than half the feature size can kill a die. At the 3nm node, that means particles as small as 1.5nm are a threat. It's why semiconductor fabs are 10,000 times cleaner than a hospital operating room.