RISC-V Processor Design and Open Source Silicon
RISC-V has gone from an academic curiosity at UC Berkeley to a processor architecture that's shipping in billions of chips. I remember when people dismissed it as a toy — something for teaching computer architecture, not for real products. Those skeptics have been thoroughly proven wrong, but the story of RISC-V's rise is more complicated and interesting than the hype suggests.
What RISC-V Actually Is (and Isn't)
RISC-V is an instruction set architecture (ISA) — the specification of what instructions a processor understands and how it encodes them. It's an open standard maintained by RISC-V International, a nonprofit organization with over 4,000 members. The base ISA is fixed (ratified and frozen), which means your code won't break when the spec evolves — new functionality comes through extensions, not changes to existing instructions.
What RISC-V is not is a chip design. The ISA says nothing about pipeline depth, cache hierarchy, branch prediction algorithms, or physical implementation. Two RISC-V processors can implement the same instruction set with wildly different performance, power, and area characteristics — just as an ARM Cortex-A78 and an ARM Cortex-M0 both implement ARM instructions but couldn't be more different as designs.
The base integer ISA (RV32I or RV64I) is deliberately minimal: 47 instructions that cover basic integer arithmetic, loads/stores, branches, and system operations. Everything else is modular:
- M extension — integer multiplication and division
- A extension — atomic memory operations (essential for multi-core)
- F/D extensions — single and double-precision floating point
- C extension — compressed 16-bit instructions (like ARM Thumb) for code density
- V extension — vector processing (ratified in 2021, this is a big one)
- B extension — bit manipulation
- H extension — hypervisor support for virtualization
The "RV64GC" designation you often see means: 64-bit base integer + General extensions (IMAFD) + Compressed instructions. This is roughly the minimum for running Linux.
The Commercial RISC-V Core Vendors
SiFive is the most prominent RISC-V core vendor, founded by the original Berkeley RISC-V creators (Krste Asanovic, Yunsup Lee, Andrew Waterman). They offer:
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- E-series — tiny embedded cores comparable to ARM Cortex-M0/M3. The E21 is a 2-stage pipeline microcontroller core.
- S-series — mid-range cores for embedded Linux. The S76 is a 5-stage, single-issue, in-order core with MMU.
- U-series — application processors. The U74 (used in the StarFive JH7110, which powers the VisionFive 2 SBC) is a dual-issue, in-order core roughly comparable to ARM Cortex-A55.
- P-series — the performance line. The P670 and P870 are out-of-order, superscalar cores targeting the Cortex-A78/A710 performance range. Intel selected the P670 for their Horse Creek reference platform.
- X-series — their highest performance line, the X280 includes a vector processing unit with configurable VLEN (vector length), targeting AI/ML and signal processing workloads.
Andes Technology (Taiwan) has been shipping RISC-V cores since 2017. Their AndesCore lineup ranges from the tiny AX25 to the high-performance AX65, with the AX45MP being popular for multi-core embedded designs. Andes has a strong presence in the Asia-Pacific market, particularly in storage controllers and networking chips.
Codasip (Czech Republic) takes a different approach with their Studio tool, which lets customers customize and extend RISC-V cores at the microarchitecture level. This appeals to companies that want more control than a fixed core provides but don't want to design from scratch.
Ventana Micro Systems is targeting the data center with their Veyron V1, a high-performance out-of-order RISC-V core designed by veterans from ARM, Intel, and Marvell. Their first product is a chiplet-based server processor aimed at cloud workloads. This is the most ambitious RISC-V effort in the server space.
Where RISC-V Is Winning Today
RISC-V's penetration varies dramatically by market segment:
Microcontrollers and embedded — this is where RISC-V has the strongest foothold. WCH's CH32V series microcontrollers (based on QingKe RISC-V cores) sell for under $0.10 in China and are used in enormous quantities. Espressif's ESP32-C3 and C6 use RISC-V cores for WiFi/Bluetooth IoT applications. GigaDevice's GD32VF103 competes with STM32 in the general-purpose MCU market. Bouffalo Lab, HPMicro, and many other Chinese companies have shipped hundreds of millions of RISC-V MCUs.
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Storage and networking — Western Digital has been a major RISC-V proponent, using SiFive cores in their SSD controllers. They've shipped over 2 billion RISC-V cores in storage products. Esperanto Technologies designed a 1,000+ core RISC-V chip for AI inference. Alibaba's T-Head division developed the Xuantie C910 core and open-sourced it, and it's used in several production chips.
Smartphones and application processors — this is where RISC-V is weakest. The software ecosystem (Android, desktop Linux, applications) is enormous and tightly optimized for ARM. Qualcomm and MediaTek are experimenting with RISC-V for auxiliary processors in their SoCs, but replacing the main application cores is years away, if it happens at all.
AI accelerators — many custom AI chips use RISC-V cores as the control processor alongside specialized compute units. The flexibility to add custom instructions for data movement, synchronization, or specialized math makes RISC-V attractive for this role.
The Software Ecosystem Gap
The biggest challenge for RISC-V isn't the hardware — it's the software. ARM has spent decades building an ecosystem of compilers, operating systems, debuggers, profilers, libraries, and trained developers. RISC-V is catching up but isn't there yet.
GCC and LLVM both support RISC-V well for compilation. Linux runs on RISC-V (Ubuntu, Fedora, Debian all have RISC-V ports). Android has experimental RISC-V support. But the optimization depth isn't the same — ARM's compiler backends have been tuned by thousands of engineers over 20+ years. RISC-V compiler output is typically 10-20% less efficient than equivalent ARM code in my benchmarks, though this gap narrows with each release.
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Debugging tools, profilers, and trace infrastructure are less mature. JTAG and OpenOCD work, but the polished integrated development environments that ARM provides through Keil, IAR, and ARM Development Studio don't have RISC-V equivalents at the same quality level. Lauterbach's TRACE32 supports RISC-V, and Segger's J-Link works with many RISC-V targets, but the ecosystem is fragmented.
Open Source Silicon: Beyond the ISA
RISC-V is part of a broader open-source silicon movement. Some notable projects:
- CHIPS Alliance — (part of the Linux Foundation) hosts open-source hardware projects including the SWeRV core family (originally from Western Digital), an open-source DRAM controller, and the Caliptra root-of-trust specification.
- OpenTitan — a collaborative effort led by lowRISC (a nonprofit spun out of the University of Cambridge) to create an open-source silicon root of trust. Google and partners designed the Earl Grey SoC, which has taped out on real silicon. This is significant because root-of-trust hardware is typically proprietary and secretive.
- PULP Platform — ETH Zurich's group has produced an impressive series of open-source RISC-V cores and SoC platforms (PULPino, PULPissimo, Ariane/CVA6) that are widely used in academic research and increasingly in industry.
- Chisel/FIRRTL — a hardware construction language developed at Berkeley that makes it easier to write parameterized, reusable hardware generators. The Rocket Chip generator (the original Berkeley RISC-V implementation) is written in Chisel, and many RISC-V cores use it.
My Take on RISC-V's Future
I think RISC-V will continue to grow rapidly in embedded and IoT. In five years, I'd expect RISC-V microcontrollers to outsell ARM Cortex-M in unit volume, driven primarily by Chinese semiconductor companies who see strategic value in an ISA that isn't controlled by a single company (especially one owned by SoftBank and subject to potential export restrictions).
In the server and PC space, I'm less certain. The software ecosystem barrier is real, and ARM has a massive head start with Apple Silicon, AWS Graviton, and Ampere processors all proving that ARM can compete with x86 in high-performance computing. RISC-V would need a "Graviton moment" — a major cloud provider or system vendor committing to deploy RISC-V at scale — to catalyze the software investment needed.
What I find most exciting isn't RISC-V as an ARM replacement, but RISC-V as an enabler of custom computing. The ability to add custom instructions (using the reserved opcode space) lets hardware designers create processors tailored to specific workloads — a genomics processor with custom alignment instructions, a network processor with built-in packet parsing operations, an audio processor with specialized DSP ops. ARM allows custom extensions too, but RISC-V's fully open nature and simpler base ISA make customization more accessible.
The open-source silicon movement is still young, and it won't replace commercial IP for most applications anytime soon. But it's creating new possibilities for education, research, and specialized applications that weren't feasible when every processor architecture was locked behind licensing fees. That alone makes it worth paying attention to.