Packaging Suddenly Fundamentals
For decades, chip packaging was an afterthought — just the plastic or ceramic shell protecting the silicon. That changed when monolithic scaling started hitting walls. You can't keep making dies bigger because yield drops exponentially with area. You can't keep shrinking transistors forever because physics gets in the way. So the industry pivoted: instead of one big chip, use multiple smaller chips (chiplets) and connect them with advanced packaging.
The three foundry giants — TSMC, Intel, and Samsung — have each developed their own advanced packaging technologies. They're all solving the same problem but with different approaches, and the differences matter for performance, cost, and availability.
TSMC CoWoS: The AI Chip Standard
Chip-on-Wafer-on-Substrate (CoWoS) is TSMC's 2.5D packaging technology, and right now it's the most commercially significant advanced packaging platform in the world. Every NVIDIA H100, H200, and B100 GPU uses CoWoS. So does AMD's Instinct MI300X.
How It Works
CoWoS places multiple dies side by side on a silicon interposer — a thin silicon wafer with through-silicon vias (TSVs) and fine-pitch metal routing. The interposer sits on top of a conventional organic substrate. Die-to-die communication happens through the interposer's wiring, which can achieve much higher density than organic substrates alone.
The latest CoWoS-S (silicon interposer variant) supports interposer sizes up to about 3,300mm² — large enough for configurations like NVIDIA's B100 with two compute dies and eight HBM3E stacks all on one interposer. The interconnect pitch on the interposer can go down to 0.4µm line/space, enabling very high bandwidth between dies.
We covered a related topic in Semiconductor Talent Crisis: Engineering Shortages and Unive.
The Capacity Problem
CoWoS capacity has been the bottleneck for AI chip supply since 2023. TSMC has been aggressively expanding — they reportedly tripled CoWoS capacity through 2024-2025 — but demand from NVIDIA, AMD, Broadcom, and others keeps outpacing supply. A CoWoS package costs significantly more than conventional packaging, adding $500-1000+ to the cost of each chip.
Intel Foveros: True 3D Stacking
Foveros is Intel's 3D face-to-face die stacking technology, first deployed in the Lakefield processor in 2020 and more recently in Meteor Lake (Core Ultra) processors.
How It Works
Unlike CoWoS's 2.5D side-by-side approach, Foveros stacks dies directly on top of each other using micro-bumps or, in newer versions, hybrid bonding. The bottom die (base tile) typically contains I/O and memory interfaces, while the top die(s) contain compute logic. TSVs through the bottom die connect everything to the package substrate below.
Foveros Direct, introduced with Intel 4 process, uses hybrid bonding with bump pitches down to 36µm — much finer than the 50-100µm micro-bumps in earlier versions. This increases the interconnect density between stacked dies dramatically, enabling more than 1,000 connections per mm².
For a related perspective, see Chiplet Architecture: UCIe, Multi-Die Design, and the Future.
EMIB: Intel's 2.5D Play
Intel also has EMIB (Embedded Multi-die Interconnect Bridge) for 2.5D integration. Instead of a full silicon interposer like CoWoS, EMIB embeds small silicon bridge chips within the organic substrate, only where die-to-die connections are needed. It's cheaper than a full interposer approach because you're only using silicon where it's actually needed. Ponte Vecchio (Intel's data center GPU) used EMIB to connect its tiles.
Samsung I-Cube and X-Cube
Samsung's advanced packaging portfolio includes I-Cube (2.5D, similar concept to CoWoS) and X-Cube (3D stacking).
I-Cube
I-Cube4, Samsung's latest 2.5D platform, supports up to four logic dies plus HBM stacks on a single silicon interposer. It's been used for HPC and AI accelerator designs from Samsung's foundry customers. The technology is broadly comparable to CoWoS-S, though Samsung's market share in this space is significantly smaller than TSMC's.
X-Cube
X-Cube stacks SRAM dies on top of logic dies using TSVs, similar in concept to Foveros. Samsung demonstrated X-Cube with their 7nm process, putting SRAM cache directly above the compute logic. The benefit is obvious — shorter wire distances to cache means lower latency and power. But the thermal challenges of stacking active logic are significant, and X-Cube hasn't seen the same volume deployment as Foveros.
This connects to the ideas in Galaxy S26 & Exynos 2600: Chip 2nm Có Đáng Tin? 2026.
Head-to-Head Comparison
For AI accelerators today, CoWoS wins on maturity and capacity — it's the proven platform with the broadest ecosystem. Intel's Foveros is technically more ambitious with true 3D stacking, but its commercial deployment has been limited to Intel's own products. Samsung's offerings are competitive on paper but lag in volume adoption.
The real differentiator going forward will be hybrid bonding — replacing solder micro-bumps with direct copper-to-copper bonds at the atomic level. This enables bump pitches below 10µm and dramatically higher interconnect density. TSMC (SoIC), Intel (Foveros Direct), and Samsung are all investing heavily here. Whoever masters hybrid bonding at volume first will have a significant advantage in the chiplet era.
I'd argue that advanced packaging is now as important as process node advancement for chip performance scaling. The "packaging wars" between these three companies will shape the semiconductor industry for the next decade at least.