Chiplets Are Reshaping How We Build Processors
The monolithic die — one giant slab of silicon with everything on it — is hitting hard physical and economic limits. Chiplet architecture breaks that single die into multiple smaller dies (chiplets) connected via an advanced packaging substrate. It's not a new idea, but it's finally becoming the standard approach for high-performance chips.
The Economics Behind the Shift
Here's the core problem with monolithic design at advanced nodes: yield. A single defect on a 600mm² die at 3nm kills the entire chip. But if you split that into four 150mm² chiplets, a defect only kills one quarter-sized piece. The math works out dramatically in your favor.
At TSMC's N3 node, a 100mm² die might achieve 80% yield. Scale that to 400mm², and yield drops to maybe 40%. But four 100mm² chiplets at 80% yield each? You get a functional set about 41% of the time, which sounds similar — until you factor in that the failed chiplets can be discarded individually rather than scrapping the whole package. Effective cost per working unit drops 30-50% depending on the design.
There's another angle too. Not everything on a chip needs the latest process node. Your CPU cores might benefit from 3nm, but the I/O controllers work perfectly fine at 6nm, which costs a fraction per square millimeter. Chiplets let you mix process nodes in a single package.
AMD's Chiplet Success Story
AMD proved the approach at scale with EPYC. Their Zen 4 EPYC processors (Genoa) pack up to 12 CCD chiplets (each containing 8 cores on TSMC 5nm) around a central IOD (I/O die on 6nm). That's 96 cores in a single socket, and the manufacturing economics make it profitable at price points that would be impossible with a monolithic design.
For a related perspective, see AI Chip 2026: NVIDIA B200 vs AMD MI455X vs Gaudi 3.
The key insight from AMD's approach: standardize the chiplet interface. Every CCD is identical — same design, same masks, same testing procedure. You bin them by quality and allocate accordingly. Server parts get the best-binned chiplets; consumer Ryzen gets a subset. One chiplet design serves an entire product lineup spanning $200 to $10,000+ SKUs.
Intel's Disaggregation Strategy
Intel's Meteor Lake was their first consumer processor to use chiplet architecture (though Intel calls them "tiles"). It separates the CPU compute tile (Intel 4), GPU tile (TSMC N5), SoC tile (TSMC N6), and I/O tile (TSMC N6). The tiles connect through Foveros 3D stacking and EMIB (Embedded Multi-die Interconnect Bridge).
Honestly, Meteor Lake's execution was mixed. The disaggregation added latency between tiles, and the first-generation implementation showed some rough edges in power management across tile boundaries. But the architecture is sound, and Arrow Lake refined it significantly.
Die-to-Die Interconnect Standards
The biggest challenge in chiplet design isn't making the individual dies — it's connecting them. You need bandwidth density comparable to what on-die wiring provides, but across a package-level interconnect.
This connects to the ideas in HBM4 Memory Technology: Architecture, Bandwidth, and the AI .
UCIe (Universal Chiplet Interconnect Express) is the industry standard that's emerging. Backed by Intel, AMD, ARM, TSMC, Samsung, and others, UCIe defines:
- Standard package interface — 28 Gbps per lane for standard bump pitch, 32 GT/s for advanced packaging
- Protocol layers supporting PCIe and CXL
- Bandwidth density up to 1317 GB/s/mm for advanced packaging configurations
- Latency targets under 2ns for die-to-die communication
UCIe 1.1 shipped in late 2023, and 2.0 is expected to push bandwidth density further. But don't expect a world where you can mix and match AMD compute chiplets with Intel I/O chiplets anytime soon — the standard handles the physical and link layers, but higher-level protocols and coherency domains remain proprietary.
TSMC's Packaging Technologies
TSMC offers a menu of chiplet packaging options, each with different tradeoffs:
CoWoS (Chip-on-Wafer-on-Substrate): The gold standard for high-bandwidth applications. Uses a silicon interposer to connect chiplets with extremely fine-pitch wiring. NVIDIA's H100 and AMD's MI300X both use CoWoS. Capacity has been a bottleneck — TSMC has been aggressively expanding CoWoS production, roughly doubling capacity each year since 2023.
See also: CXL Memory Expansion: Disaggregated Memory Pools and Compute.
InFO (Integrated Fan-Out): Lower cost than CoWoS, using a redistribution layer instead of a silicon interposer. Apple's been using InFO variants since the A10 chip. Good enough for many applications but can't match CoWoS on interconnect density.
SoIC (System on Integrated Chips): True 3D stacking with direct bonding — sub-micron bump pitch, enabling bandwidth densities that blow 2.5D solutions away. Still ramping in production, but this is where the industry is heading.
The Design Challenges Nobody Talks About
Chiplet architecture creates problems that monolithic designs never had. Thermal management gets complicated when you stack or tightly pack multiple heat-generating dies. Power delivery needs to feed multiple dies through the package substrate, and voltage droop becomes harder to manage. Testing is more complex — you need Known Good Die (KGD) testing to avoid packaging bad chiplets, and the test infrastructure for that isn't cheap.
EDA tools are also playing catch-up. Most chip design tools were built for monolithic flows. Multi-die design requires co-simulation across chiplet boundaries, package-aware timing analysis, and thermal-mechanical co-design that existing tools handle awkwardly at best.
Where This Goes Next
The trajectory is clear: more chiplets, denser interconnects, and true 3D integration. AMD's next-generation EPYC (Turin) pushes the chiplet count higher. NVIDIA's next GPU architecture will likely increase its use of chiplets. And the entire AI accelerator market is converging on multi-die designs because single dies simply can't contain enough HBM interfaces and compute in one piece of silicon.
I'd argue the most interesting development isn't technical — it's business model. If UCIe matures enough, we could see a market for third-party chiplets. Imagine buying compute chiplets from one vendor, I/O from another, and custom accelerator chiplets from a startup, all assembled into a single package. We're probably five to seven years from that reality, but the technical foundations are being laid right now.