3D NAND Flash: Layer Stacking, String Architecture, and the Road to 300+ Layers

FPGA vs ASIC Decision Framework for AI Workloads

I've been through the FPGA-vs-ASIC decision process more times than I can count, and every time, the conversation starts the same way: someone insists FPGAs are "flexible" and ASICs are "fast," as if that settles it. It doesn't. The actual decision involves unit economics, time-to-market pressure, workload stability, and a realistic assessment of your team's capabilities. Let me share how I think about this for AI-specific workloads.

Understanding the Cost Crossover

The classic FPGA-vs-ASIC crossover analysis comes down to NRE (non-recurring engineering) costs versus per-unit costs. An ASIC at a 7nm node costs $30-80 million in NRE (mask sets alone are $15-20 million at TSMC N7). An FPGA costs zero NRE — you're paying for someone else's NRE amortized across all their customers.

Here's a rough framework I use:

• Below 10,000 units: FPGA almost always wins on total cost unless you can use an older, cheaper ASIC node.
• 10,000-100,000 units: Gray zone. Depends heavily on the per-unit FPGA cost. A Xilinx (AMD) Versal VCK190 board costs $4,000+. If your ASIC can be done on a 28nm node with $5-10M NRE, the crossover might be at 20,000 units.
• Above 100,000 units: ASIC is almost certainly cheaper per unit. The per-die cost of an ASIC at any modern node is a fraction of an equivalent FPGA.
• Above 1 million units: FPGA doesn't even make sense. The volume economics overwhelmingly favor ASIC.

But this purely financial analysis misses the nuance. Let me dig into the AI-specific considerations.

The AI Workload Stability Question

This is, I think, the most important factor that gets underweighted. AI models change constantly. The model architecture that's modern today may be replaced in 12 months. If you're building an ASIC for transformer inference in 2024, you might find by 2026 that the dominant architecture is a state-space model (like Mamba) or a hybrid architecture that your hardwired attention accelerator can't handle efficiently.

See also: SRAM Cell Design: Bitcell Scaling, Read Stability, and Embed.

FPGAs give you reconfigurability. You can redesign the compute pipeline in firmware without changing hardware. Xilinx's Vitis AI toolchain lets you compile neural network models into FPGA bitstreams with reasonable productivity, and AMD's Alveo V80 accelerator card supports INT8 inference at around 400 TOPS.

But here's the counterargument: the fundamental operations in neural networks haven't changed much. It's still matrix multiply, activation functions, normalization, and data shuffling. The exact shapes and sizes change, but a well-designed ASIC with a programmable dataflow (like a systolic array with configurable dimensions) can handle a wide range of models. NVIDIA's tensor cores are technically "fixed function" but handle everything from CNNs to transformers to diffusion models because they accelerate the common operation (matrix multiply) rather than a specific model architecture.

Performance and Power: Where ASICs Win

An FPGA implements logic using look-up tables (LUTs), configurable logic blocks (CLBs), and programmable routing. This flexibility comes at a cost: roughly 10-40x more area, 3-10x more power, and 3-5x worse clock frequency compared to a hardwired ASIC implementation of the same function.

For a concrete example: a 16x16 INT8 multiply-accumulate unit in an ASIC at TSMC 7nm might occupy 0.01mm2 and run at 1.5GHz consuming 5mW. The same function mapped to an FPGA's DSP slices and LUTs might use 0.1mm2 equivalent area and achieve 500MHz at 30mW. Those gaps add up fast when you're instantiating thousands of MAC units.

For a related perspective, see Semiconductor Testing and Packaging Outsourcing: OSAT Indust.

Modern FPGAs try to close this gap with hardened blocks. AMD's Versal AI Core devices include AI Engine tiles — hardened vector processors (not programmable logic) that deliver much better TOPS/W than LUT-based implementations. Intel's Agilex devices have hardened tensor blocks. These are essentially small ASICs embedded in an FPGA fabric, which somewhat undermines the pure "flexibility" argument for FPGAs.

Time-to-Market Analysis

An FPGA-based AI accelerator can go from concept to working silicon in 6-12 months if you have experienced RTL engineers. You're writing HDL (Verilog/VHDL or using HLS tools), simulating, synthesizing for the FPGA target, and running on real hardware within weeks of starting.

An ASIC takes 18-36 months from architecture to production silicon. The design phase is similar, but you add physical design (place-and-route at the transistor level), timing closure, DRC/LVS verification, tape-out, mask fabrication (8-12 weeks), wafer fabrication (12-16 weeks for advanced nodes), packaging, and testing. If you find a bug after tape-out, a mask re-spin costs millions and adds 6+ months.

I've seen many companies start with an FPGA prototype to validate their AI architecture and algorithm, then migrate to an ASIC once the design is proven and they have volume to justify the NRE. This is honestly the most sensible approach for startups. Companies like Mobileye (now Intel) did exactly this — prototyped their vision algorithms on FPGAs, then built the EyeQ ASIC family once the architecture stabilized.

We covered a related topic in Semiconductor Industry Cycles: Boom, Bust, and Demand Foreca.

The FPGA-to-ASIC Migration Path

One hybrid approach worth mentioning: structured ASICs or FPGA-to-ASIC conversion services. Intel (formerly Altera) offered eASIC, which takes an FPGA design and implements it in a simplified ASIC flow using metal-programmable gate arrays. The NRE is much lower than a full custom ASIC ($1-5M vs $30M+), and you get 2-3x the performance and power improvement over the FPGA. The trade-off is that you don't get the full 10x benefit of a custom ASIC.

AMD (Xilinx) has a similar program for converting Versal designs to hardened implementations. These middle-ground options make sense for volumes in the 50,000-500,000 range where full ASIC NRE is hard to justify but FPGA per-unit costs are too high.

My Decision Framework

When I consult on FPGA-vs-ASIC decisions for AI products, I walk through these questions in order:

1. What's your expected production volume over 3 years? — Below 50K units, start with FPGA unless power is absolutely critical. Above 500K units, plan for ASIC from the start.
2. How stable is your target workload? — If you're building for a specific model that won't change (embedded vision with a fixed YOLOv5 model), ASIC makes sense. If you need to support arbitrary user-defined models, the flexibility argument for FPGAs is strong.
3. What's your power budget? — If you have a hard 5W limit and need 100 TOPS, an FPGA won't get you there. Period. You need an ASIC or a purpose-built accelerator chip.
4. What's your team's expertise? — ASIC design requires physical design, DFT (design for testability), and foundry interaction skills that many teams don't have. You'll need to hire or contract with an ASIC design house (like Synopsys DWC, Faraday, or Global Unichip). FPGA design is more accessible, though still demanding.
5. What's your funding situation? — ASIC NRE of $30-80M means you need significant capital before you have a working chip. FPGA lets you start with a working product and revenue before committing to ASIC.
6. What's the competitive timeline? — If being first to market matters — and in AI, it usually does — an FPGA prototype shipped in 9 months beats an ASIC that's 18 months away.

Real-World Examples

A few companies that illustrate different points on this spectrum:

• Microsoft Project Brainwave initially deployed Intel Stratix 10 FPGAs for real-time AI inference in Azure. They chose FPGAs because the model types and sizes changed frequently, and they needed to support customer-defined models. They've since moved toward custom ASICs (Maia) for their highest-volume internal workloads while keeping FPGAs for flexible inference.
• Tesla went straight to ASIC (FSD chip, now HW4/HW5) because they have millions of units (every car they sell) and a fixed neural network architecture they control end-to-end. The economics are obvious at that volume.
• Lattice Semiconductor targets low-power AI at the far edge (always-on keyword detection, presence sensing) with small FPGAs like the Lattice Nexus platform. At under 1W, these are too power-constrained for a custom ASIC to make economic sense given the application volumes.

There's no universal right answer. But if you're honest about your volumes, your workload stability, and your team's capabilities, the decision usually becomes clear.