Power Is the Constraint
For the past 15 years, chip performance has been limited not by transistor speed but by power dissipation. A modern desktop processor can burn over 250 watts. A smartphone SoC has a thermal budget of 3-5 watts. In both cases, the chip could go faster if it could dissipate more heat. Power management — the collection of techniques that dynamically balance performance and power consumption — is what determines how much performance you actually extract from the silicon.
Dynamic Voltage and Frequency Scaling (DVFS)
DVFS is the most fundamental power management technique. The dynamic power of a CMOS circuit follows the equation P = α × C × V² × f, where α is the activity factor, C is the switched capacitance, V is the supply voltage, and f is the clock frequency. Since voltage and frequency are roughly proportional (higher voltage enables higher frequency), power scales approximately with V³. Cut the voltage by 20% and you cut power roughly in half — at the cost of lower clock speed.
Operating Performance Points
Processors define discrete voltage-frequency pairs called operating performance points (OPPs) or P-states. A typical mobile SoC might have 10-20 OPPs ranging from 400 MHz at 0.55V (lowest power) to 3.3 GHz at 1.05V (maximum performance). The power management unit (PMU) selects the appropriate OPP based on workload demand, thermal headroom, and battery state.
The voltage regulators that supply the core voltage need to respond quickly — on the order of microseconds — to track OPP transitions. Integrated voltage regulators (IVRs), where the regulator is on the same die as the processor, enable faster transitions than discrete off-chip regulators. Intel's Haswell was one of the first to use fully integrated voltage regulation, though the approach has tradeoffs in efficiency and die area.
Per-Core and Per-Cluster DVFS
Early DVFS implementations applied the same voltage and frequency to all cores. Modern designs allow independent voltage and frequency for each core or core cluster. This matters because workloads are rarely symmetric — one core might be handling a demanding foreground task at high frequency while others idle at minimum power. Apple's M-series chips and Qualcomm's Snapdragon both support per-core DVFS.
See also: Foundry Business Model: How TSMC, Samsung, and Intel Foundry.
Power Gating
DVFS controls active power. Power gating addresses leakage power — the current that flows through transistors even when they're not switching. At advanced process nodes, leakage can represent 30-40% of total power. Power gating uses header or footer switches (large transistors) to disconnect idle blocks from the power supply entirely, reducing their leakage to near zero.
The Wake-Up Cost
Power gating isn't free. When a block is power-gated, all its state (register contents, SRAM data) is lost unless saved beforehand. Waking up a power-gated block takes time — the power supply must ramp up, the logic must initialize, and any saved state must be restored. This wake-up latency ranges from microseconds to milliseconds depending on the block size and how much state needs restoration.
There's a break-even point: power gating only saves energy if the idle period is long enough to offset the energy cost of the power-down and wake-up transitions. For cores that frequently transition between active and idle, the overhead can actually waste more energy than it saves. Getting the power gating policy right — when to gate and when to keep a block in a low-power but responsive state — requires careful workload analysis.
Retention Power Gating
Some designs use retention cells that maintain register state even when the main power supply is gated off. These cells use a separate, always-on power rail and special flip-flops with built-in state storage. Retention dramatically reduces wake-up latency (no need to reload state) at the cost of slightly higher leakage than full power gating and increased cell area.
For a related perspective, see Backside Power Delivery: Why Routing Power Under the Transis.
Thermal Throttling
When a chip's temperature exceeds safe limits (typically 95-105°C for consumer processors, 85-100°C for server chips), it must reduce its power output. This is thermal throttling.
PROCHOT and Thermal Monitors
Modern processors have dozens of on-die thermal sensors distributed across the chip. Intel CPUs use Digital Thermal Sensors (DTS) that report temperature relative to the thermal junction temperature (Tj,max). When any sensor hits the threshold, the processor can reduce frequency (soft throttling), enable duty cycling (hard throttling, where the clock is periodically gated off), or in extreme cases, shut down entirely to prevent physical damage.
The Thermal Design Game
Processor vendors play a sophisticated game with thermal specifications. Intel's PL1 (Power Level 1) is the sustained power limit — the thermal design power (TDP) that the cooling solution must handle continuously. PL2 is a higher burst power limit that the processor can sustain for a short period (typically 28-56 seconds). PL2 on a 125W TDP desktop chip might be 253W — more than double the sustained limit.
In practice, a well-cooled system running a sustained workload will settle at a power level determined by the thermal equilibrium between heat generation and cooling capacity. A beefy tower cooler might let a chip sustain PL2 indefinitely. A thin laptop cooler might throttle below PL1 within minutes. The same chip can perform very differently depending on what's attached to the other side of the heatspreader.
For a related perspective, see Snapdragon 8 Gen 5 Review: Full Architecture Deep Dive and B.
Advanced Techniques
Adaptive Voltage
Not all chips are created equal. Silicon manufacturing variation means one chip might run at 1.0V where another needs 1.05V for the same frequency. Adaptive voltage techniques measure each chip's actual voltage requirements and adjust accordingly. Intel's Adaptive Boost Technology and AMD's Precision Boost Overdrive both exploit this — chips that won the silicon lottery can run at higher frequencies or lower voltages than the guaranteed specification.
Race-to-Sleep
Counterintuitively, running at maximum performance can sometimes save energy. If a task completes 2x faster at 2x the power, the total energy (power × time) is the same — but the processor can then power-gate completely while waiting for the next task. For bursty workloads (like responding to a touch event on a phone), race-to-sleep at high frequency followed by deep sleep is more efficient than running slowly and staying awake longer.
Power management is one of those areas where the hardware-software boundary blurs completely. The OS scheduler, the firmware, the hardware power controller, and the voltage regulators all interact in a closed loop that runs millions of times per second. Getting it right means better battery life, higher sustainable performance, and lower electricity bills in data centers. Getting it wrong means throttled performance, dead batteries, and overheating devices.