Gate-All-Around vs FinFET: The Transistor Architecture Shift
Every processor you've used in the last decade was built with FinFET transistors. That era is ending. Gate-all-around (GAA) nanosheet transistors are replacing FinFETs at the 2nm node and beyond. This isn't an incremental improvement — it's the most significant change in transistor architecture since FinFET itself replaced planar transistors in 2011.
How FinFET Works (And Its Limits)
A FinFET transistor's channel (the region where current flows) is shaped like a vertical fin rising from the silicon surface. The gate wraps around three sides of this fin, providing much better control over the channel than the flat gate of a planar transistor. Intel introduced this at 22nm in 2011, and it's been the standard architecture through 3nm.
But FinFETs have scaling problems. The fin width can't be easily varied — it's essentially fixed by the manufacturing process, typically 5-7nm at advanced nodes. To increase drive current (make a faster transistor), you add more fins. But each fin takes space, and at some point you can't fit enough fins in the area budget while maintaining the pitch spacing that defines the node density.
At 3nm, a typical logic transistor has 2-3 fins per device. The fins are so thin that quantization effects start to matter — current flow through a 5nm-wide silicon fin is dominated by quantum mechanical effects rather than classical semiconductor physics. Variability between fins becomes a significant source of performance spread across the chip.
GAA Nanosheet Architecture
Gate-all-around takes the channel control concept to its logical conclusion: the gate completely surrounds the channel on all four sides. In the nanosheet variant (the implementation all three major foundries are using), the channel consists of multiple thin sheets of silicon stacked vertically, with gate material filling the gaps between and surrounding each sheet.
A typical GAA nanosheet transistor has 3-4 stacked sheets, each approximately 5-7nm thick and variable width. This variable width is GAA's key advantage over FinFET. By adjusting the nanosheet width, designers can tune drive current continuously — wide sheets for high-performance paths, narrow sheets for low-power paths — within the same process technology.
We covered a related topic in Chip 2nm là gì? Tổng quan Công nghệ Bán dẫn Thế hệ Mới 2026.
This width tunability doesn't exist in FinFETs, where the fin width is fixed and the only way to increase drive current is adding more fins. GAA gives circuit designers a new degree of freedom that can be used to optimize power-performance-area (PPA) trade-offs at the individual transistor level.
Manufacturing Challenges
Building a GAA nanosheet transistor requires several new process steps that FinFET doesn't need:
Superlattice growth: The nanosheet stack starts as alternating layers of silicon and silicon-germanium (SiGe), grown epitaxially. The SiGe layers are sacrificial — they'll be selectively removed later to create the gaps where gate material is deposited. The thickness uniformity of these layers across a 300mm wafer needs to be controlled to sub-nanometer precision.
Channel release: Selectively etching away the SiGe layers without attacking the silicon nanosheets is a delicate process. The etch chemistry needs extreme selectivity — removing SiGe at 100× the rate of Si while maintaining the geometric integrity of nanosheets that are only 5nm thick.
Inner spacer formation: After removing the SiGe, insulating spacers must be deposited in the gaps between nanosheets to isolate the gate from the source and drain contacts. These inner spacers need to be uniform in thickness (a few nanometers) across all gaps in all transistors on the wafer. This step has been one of the biggest yield challenges in early GAA production.
This connects to the ideas in Chip Design Flow: RTL to GDSII and the Electronic Design Aut.
Gate deposition: Filling the narrow gaps between nanosheets with gate metal and high-k dielectric requires atomic layer deposition (ALD) with excellent conformality — the film needs to coat all surfaces uniformly, including the bottom surfaces of upper nanosheets.
Samsung's Early GAA Experience
Samsung was first to market with GAA at their 3nm node (SF3E), shipping in 2022. Honestly, the early results were mixed. Yield was lower than their FinFET-based 4nm process, and the performance improvement didn't match initial projections. Several high-profile customers (notably Qualcomm) chose TSMC's FinFET-based 3nm node instead.
Samsung's challenges highlight the difficulty of introducing GAA. The process complexity adds roughly 15-20% more steps compared to an equivalent FinFET flow, each with its own yield impact. The learning curve is steep, and Samsung bore the cost of being first.
That said, Samsung's second-generation 3nm GAA (SF3) showed significant improvements, and their 2nm (SF2) benefits from the accumulated learning. Being the first mover had costs, but it also built expertise that competitors are only now developing.
Performance Comparison
At matched technology nodes, GAA nanosheets offer:
For a related perspective, see HBM4 Memory Technology: Architecture, Bandwidth, and the AI .
- 5-15% higher drive current at the same voltage (from better gate control)
- 15-25% lower leakage current (again, better gate control reduces off-state current)
- The width-tunability flexibility that FinFET simply can't match
- Better short-channel effects control at extremely scaled gate lengths
These numbers come from foundry presentations and should be taken with appropriate skepticism — they're measured on test structures under ideal conditions. Real chip performance depends on many factors beyond the transistor itself: interconnect resistance, power delivery, thermal effects, and the specific circuit design.
Beyond Nanosheets: Forksheet and CFET
GAA nanosheets won't be the last word in transistor architecture. Research is already underway on next-generation structures:
Forksheet transistors: Place NMOS and PMOS transistor stacks closer together by sharing a common wall between them. This increases density by reducing the separation between complementary transistor pairs. Imec has demonstrated forksheet concepts targeting nodes beyond 2nm.
CFET (Complementary FET): Stack the NMOS transistor directly on top of the PMOS transistor (or vice versa). This could theoretically double the transistor density of nanosheets by using the vertical dimension. The manufacturing challenges are extreme — you're building two complete transistors vertically, with precise alignment and different channel materials for each.
These are 2030+ technologies at the earliest. For the next five years, GAA nanosheets with incremental improvements (more sheets, tighter pitch, backside power delivery) will be the workhorse architecture for leading-edge chips.
The Bottom Line
GAA nanosheet transistors are a genuine improvement over FinFETs — not a revolution, but a meaningful step forward in transistor performance, power efficiency, and design flexibility. The transition is happening across the industry in 2025-2026, driven by the physics requirement for better channel control at sub-3nm dimensions. The early growing pains (particularly Samsung's experience) are normal for any major architecture transition, and the long-term benefits are well-established in both simulation and silicon.